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PDF EMP8041-33VF05NRR Data sheet ( Hoja de datos )

Número de pieza EMP8041-33VF05NRR
Descripción Low-Dropout Linear Regulator
Fabricantes Elite Semiconductor 
Logotipo Elite Semiconductor Logotipo



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No Preview Available ! EMP8041-33VF05NRR Hoja de datos, Descripción, Manual

ESMT/EMP
EMP8041
High Input Voltage, Low Quiescent Current,
Low-Dropout Linear Regulator
General Description
The EMP8041 is a high voltage, low quiescent current,
low dropout regulator with 100mA output driving
capacity. The EMP8041, which operates over an
input range of 3V to 36V, is stable with any
capacitors, whose capacitance is larger than 1μF,
and suitable for powering battery-management ICs
because of the virtue of its low quiescent current
consumption and low dropout voltage. Below the
maximum power dissipation (please refer to Note. 5),
It guarantees delivery of 100mA output current, and
supports preset output voltages ranging from 1.3V to
6.0V with 0.1V increment.
EMP8041 features also include bandgap voltage
reference, constant current limiting and thermal
overload protection. Both miniature SOT-23-5 and
SOT-89-3 package options are offered to provide
flexibility for different applications.
Applications
g Logic Supply for High Voltage Batteries
g Keep-Alive Supply
g 3-4 Cell Li-ion Batteries Powered systems
Features
g 100mA guaranteed output current (without
thermal limit)
g 500mV typical dropout at Io=100mA
g 12µA typical quiescent current
g 1µA typical shutdown mode
g 3.0V to 36V input range
g Stable with small ceramic output capacitors
(1µF)
g Over temperature and over current
protection
g ±2.5% output voltage tolerance
Typical Application
Elite Semiconductor Memory Technology Inc./Elite MicroPower Inc.
Publication Date: Feb. 2010
Revision: 1.0
1/13

1 page




EMP8041-33VF05NRR pdf
ESMT/EMP
EMP8041
Note 1: Absolute maximum ratings indicate limits beyond which damage may occur.
Note 2: All voltages are in respect to the potential of the ground pin.
Note 3: θJA is measured in the natural convection at TA=25on a high effectively thermal conductivity test board (2
layers, 2S0P).
Note 4: θJC represents the resistance between the chip and the top of the package case.
Note 5: Maximum power dissipation for the device is calculated using the following equation:
PD
=
TJ(MAX)
θJA
-
TA
Where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the
junction-to-ambient thermal resistance. For example, for the SOT-89-3 packageθJA=90°C/W, TJ(MAX)=160°C
and using TA=25°C, the maximum power dissipation is 1.5W.
The derating factor (-1/θJA)=-11.1mW/°C. Below 25°C the power dissipation figure can be increased by
11.1mW per degree and similarly decreased by this factor for temperatures above 25°C.
Note 6: Typical values represent the most likely parametric norm.
Note 7: Dropout voltage is measured by reducing VIN until VOUT drops to 98% its nominal value.
Elite Semiconductor Memory Technology Inc./Elite MicroPower Inc.
Publication Date: Feb. 2010
Revision: 1.0
5/13

5 Page





EMP8041-33VF05NRR arduino
ESMT/EMP
Package Outline Drawing
SOT-89-3
EMP8041
SYMBPLS
A
B
B1
C
D
D1
E
H
E
e1
L
MIN.
1.40
0.44
0.36
0.35
4.40
1.35
2.29
3.94
0.89
NOM. MAX.
1.60
0.56
0.48
0.44
4.60
1.83
2.60
4.25
1.50 BSC
3.00 BSC
1.2
UNIT: MM
Elite Semiconductor Memory Technology Inc./Elite MicroPower Inc.
Publication Date: Feb. 2010
Revision: 1.0
11/13

11 Page







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