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PDF EMP8130-28VN05NRR Data sheet ( Hoja de datos )
| Número de pieza | EMP8130-28VN05NRR | |
| Descripción | 300mA CMOS Linear Regulator | |
| Fabricantes | Elite Semiconductor | |
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ESMT
Preliminary
EMP8130
Ultra High-PSRR, Low-Noise, 300mA CMOS
Linear Regulator
General Description
The EMP8130 features ultra-high power supply
rejection ratio, low output voltage noise, low
dropout voltage, low quiescent current and fast
transient response. It guarantees delivery of 300mA
output current and supports preset output voltages
ranging from 0.8V to 4.0V with 0.1V increment.
Applications
g Wireless handsets
g PCMCIA cards
g DSP core power
g Hand-held instruments
g Battery-powered systems
g Portable information appliances
Based on its low quiescent current consumption and
its less than 1uA shutdown mode of logical operation,
the EMP8130 is ideal for battery-powered
applications. The high power supply rejection ratio
of the EMP8130 holds well for low input voltages
typically encountered in battery-operated systems.
The regulator is stable with small ceramic capacitive
loads (1µF typical).
The EMP8130 is available in miniature SOT-23-5
package.
Features
g 300mA guaranteed output current
g 75dB typical PSRR at 1kHz
g 260mV (VOUT=3.3V) typical dropout at 300mA
g 52µA typical quiescent current
g Less than 1µA typical shutdown mode
g Fast line and load transient response
g 1.7V to 5.5V input range
g Auto-discharge during chip disable
g 0.8V to 4.0V output voltage range
g Stable with small ceramic output capacitors
g Fold-back over current protection
g ±1% output voltage tolerance
Typical Application
EMP8130
VIN
1uF
Ceramic
Capacitor
IN OUT
ON/OFF
EN
GND
VOUT
1uF
Ceramic
Capacitor
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2014
Revision: 0.1
1/12
1 page  
ESMT
Preliminary
EMP8130
Note 1: Absolute Maximum ratings indicate limits beyond which damage may occur. Electrical specifications do not
apply when operating the device outside of its rated operating conditions.
Note 2: All voltages are with respect to the potential at the ground pin.
Note 3: θJA is measured in the natural convection at TA=25℃ on a high effective thermal conductivity test board (2
layers, 2S0P).
Note 4: θJC represents the resistance to the heat flows the chip to package top case.
Note 5: Dropout voltage is measured by reducing VIN until VOUT drops 100mV from its nominal value at VIN -VOUT = 1V.
Note 6: Maximum Power dissipation for the device is calculated using the following equations:
PD
=
TJ(MAX)
θJA
-
TA
Where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the
junction-to-ambient thermal resistance. E.g. for the SOT-23-5 packageθJA = 152°C/W, TJ (MAX) = 150°C and
using TA = 25°C, the maximum power dissipation is found to be 0.82W. The derating factor (-1/θJA) =
-6.6mW/°C, thus below 25°C the power dissipation figure can be increased by 6.6mW per degree, and
similarity decreased by this factor for temperatures above 25°C.
Note 7: Typical values represent the most likely parametric norm.
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2014
Revision: 0.1
5/12
5 Page 
ESMT
Revision History
Revision
0.1
Preliminary
EMP8130
Date
2014.02.11
Initial version.
Description
Elite Semiconductor Memory Technology Inc.
Publication Date: Feb. 2014
Revision: 0.1
11/12
11 Page | ||
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