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AX1250ES 데이터시트 PDF




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부품번호 AX1250ES 기능
기능 2A Sink/Source Bus Termination Regulator
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AX1250ES 데이터시트, 핀배열, 회로
AX1250ES
2A Sink/Source Bus Termination Regulator
GENERAL DESCRIPTION
The AX1250ES is a simple, cost-effective and high-speed linear regulator designed
to generate termination voltage in double data rate (DDR) memory system to comply with
the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and
SCSI-3 etc. devices requirements. The regulator is capable of actively sinking or sourcing
up to 2A while regulating an output voltage to within 40mV. The output termination voltage
cab be tightly regulated to track 1/2VDDQ by two external voltage divider resistors or the
desired output voltage can be programmed by externally forcing the REFEN pin voltage.
The AX1250ES also incorporates a high-speed differential amplifier to provide
ultra-fast response in line/load transient. Other features include extremely low initial offset
voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal
shut-down protection.
The AX1250ES are available in the SOP-8L-EP (Exposed Pad) surface mount
packages.
FEATURES
- Ideal for DDR-I, DDR-II and DDR-III VTT Applications
- Sink and Source 2A Continuous Current
- Integrated Power MOSFETs
- Generates Termination Voltage for SSTL_2, SSTL _18, HSTL, SCSI-2 and SCSI-3
Interfaces.
- High Accuracy Output Voltage at Full-Load
- Output Voltage traces REFEN Pin Voltage.
- Low External Component Count
- Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output
- Current Limiting Protection
- Thermal Shutdown Protection
- SOP-8L with exposed pad Pb-Free Package.
1/9
Axelite Confidential Materials, do not copy or distribute without written consent.
Rev.1.3 Aug.24, 2011




AX1250ES pdf, 반도체, 판매, 대치품
APPLICATION CIRCUIT
AX1250ES
APPLICATION INFORMATION
Input Capacitor and Layout Consideration
Place the input bypass capacitor as close as possible to the AX1250ES. A low ESR
capacitor larger than 470uF is recommended for the input capacitor. Use short and wide
traces to minimize parasitic resistance and inductance. Inappropriate layout may result in
large parasitic inductance and cause undesired oscillation between AX1250ES and the
preceding power converter.
Consideration while designs the resistance of voltage divider
Make sure the sinking current capability of pull-down NMOS if the lower resistance
was chosen so that the voltage on VREFEN is below 0.2V. In addition, the capacitor and
voltage divider form the low pass filter. There are two reasons doing this design; one is
for output voltage soft-start while another is for noise immunity.
Terminator Resistor
R0
BUS(0)
REFEN
AX1250ES VOUT
R1
BUS(1)
R2 BUS(2)
R3 BUS(3)
R4 BUS(4)
R5 BUS(5)
AX1250ES VOUT
R6 BUS(6)
R7 BUS(7)
R8 BUS(8)
R9 BUS(9)
R(2N)
R(2N+1)
BUS(2N)
BUS(2N+1)
4/9
Axelite Confidential Materials, do not copy or distribute without written consent.
Rev.1.3 Aug.24, 2011

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AX1250ES 전자부품, 판매, 대치품
AX1250ES
TYPICAL CHARACTERISTICS (COUNTINOUS)
DDR-II
DDR-II
DDR-I
DDR-I
DDR-II
DDR-II
7/9
Axelite Confidential Materials, do not copy or distribute without written consent.
Rev.1.3 Aug.24, 2011

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관련 데이터시트

부품번호상세설명 및 기능제조사
AX1250ES

2A Sink/Source Bus Termination Regulator

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