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HCPL-0601 데이터시트 PDF




Fairchild Semiconductor에서 제조한 전자 부품 HCPL-0601은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 HCPL-0601 기능
기능 HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS
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HCPL-0601 데이터시트, 핀배열, 회로
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
HCPL-0600
HCPL-0601
DESCRIPTION
The HCPL-0600/0601optocouplers consist of a 870 nm AlGaAS LED, optically coupled to a very high speed integrated photo-
detector logic gate with a strobable output. The devices are housed in a compact small-outline package. This output features an
open collector, thereby permitting wired OR outputs. The coupled parameters are guaranteed over the temperature range of -40°C
to +85°C. A maximum input signal of 5 mA will provide a minimum output sink current of 13 mA (fan out of 8). An internal noise
shield provides superior common mode rejection of typically 10 kV/µs.
FEATURES
• Compact SO8 package
• Very high speed-10 MBit/s
• Superior CMR-10 kV/µs
• Fan-out of 8 over -40°C to +85°C
• Logic gate output
• Strobable output
• Wired OR-open collector
• U.L. recognized (File # E90700)
APPLICATIONS
• Ground loop elimination
• LSTTL to TTL, LSTTL or
5-volt CMOS
• Line receiver, data transmission
• Data multiplexing
• Switching power supplies
• Pulse transformer replacement
• Computer-peripheral interface
N/C 1
+2
V
F
_3
N/C 4
8
V
CC
7
V
E
6V
O
5 GND
Single-channel
circuit drawing
PACKAGE DIMENSIONS
0.164 (4.16)
0.144 (3.66)
Pin 1
0.202 (5.13)
0.182 (4.63)
0.143 (3.63)
0.123 (3.13)
0.019 (0.48)
0.010 (0.25)
0.006 (0.16)
0.021 (0.53)
0.011 (0.28)
0.008 (0.20)
0.003 (0.08)
0.050 (1.27)
TYP
0.244 (6.19)
0.224 (5.69)
Lead Coplanarity : 0.004 (0.10) MAX
NOTE
All dimensions are in inches (millimeters)
TRUTH TABLE
(Positive Logic)
Input
H
L
H
L
H
L
Enable
H
H
L
L
NC
NC
A 0.1 µF bypass capacitor must be connected between pins 8 and 5. (See note 1)
Output
L
H
H
H
L
H
© 2003 Fairchild Semiconductor Corporation
Page 1 of 12
4/10/03




HCPL-0601 pdf, 반도체, 판매, 대치품
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
HCPL-0600
HCPL-0601
TRANSFER CHARACTERISTICS (TA = -40°C to +85°C Unless otherwise specified.)
DC Characteristics
Test Conditions Symbol
Min
Typ**
High Level Output Current
Low Level Output Voltage
Input Threshold Current
(VCC = 5.5 V, VO = 5.5 V)
(IF = 250 µA, VE = 2.0 V) (Note 2)
(VCC = 5.5 V, IF = 5 mA)
(VE = 2.0 V, IOL = 13 mA) (Note 2)
(VCC = 5.5 V, VO = 0.6 V,
VE = 2.0 V, IOL = 13 mA)
IOH
VOL
IFT
.35
3
Max
100
0.6
5
Unit
µA
V
mA
ISOLATION CHARACTERISTICS (TA = -40°C to +85°C Unless otherwise specified.)
Characteristics
Test Conditions Symbol Min
Typ**
Max
Unit
Input-Output
Insulation Leakage Current
(Relative humidity = 45%)
(TA = 25°C, t = 5 s)
(VI-O = 3000 VDC)
(Note 11)
II-O
1.0* µA
Withstand Insulation Test Voltage
(RH < 50%, TA = 25°C)
(Note 11) ( t = 1 min.)
Resistance (Input to Output)
Capacitance (Input to Output)
(VI-O = 500 V) (Note 11)
(f = 1 MHz) (Note 11)
** All typical values are at VCC = 5 V, TA = 25°C
VISO
RI-O
CI-O
2500
1012
0.6
VRMS
pF
NOTES
1. The VCC supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic or solid
tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package VCC
and GND pins of each device.
2. Enable Input - No pull up resistor required as the device has an internal pull up resistor.
3. tPLH - Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current pulse to the
1.5V level on the LOW to HIGH transition of the output voltage pulse.
4. tPHL - Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current pulse to the
1.5V level on the HIGH to LOW transition of the output voltage pulse.
5. tr - Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.
6. tf - Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.
7. tELH - Enable input propagation delay is measured from the 1.5V level on the HIGH to LOW transition of the input voltage pulse
to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.
8. tEHL - Enable input propagation delay is measured from the 1.5V level on the LOW to HIGH transition of the input voltage pulse
to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.
9. CMH - The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e.,
VOUT > 2.0 V). Measured in volts per microsecond (V/µs).
10. CML - The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the low output state
(i.e., VOUT < 0.8 V). Measured in volts per microsecond (V/µs).
11. Device considered a two-terminal device: Pins 1,2,3 and 4 shorted together, and Pins 5,6,7 and 8 shorted together.
© 2003 Fairchild Semiconductor Corporation
Page 4 of 12
4/10/03

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HCPL-0601 전자부품, 판매, 대치품
HCPL-0600
HIGH SPEED-10 MBit/s
LOGIC GATE OPTOCOUPLERS
HCPL-0601
Fig. 9 Typical Enable Propagation Delay vs. Temparature
90
Vcc = 5.0 V
VEH= 3.0 V
VEL = 0 V
IF = 7.5 mA
60
tELH, RL = 1 k
30 tELH, RL = 350
tEHL, RL = 350 Ω, 1 k
0
-60 -40 -20 0 20 40 60
TA - TEMPERATURE (˚C)
80 100
Fig. 10 Typical Rise and Fall Time vs. Temperature
180
160 Vcc = 5.0 V
IF = 7.5 mA
140
120
RL = 1 k
100
80 RL = 350
60
40 RL = 350 Ω, 1 k
20
0
-60 -40 -20 0 20 40 60
TA - TEMPERATURE (˚C)
tRISE
tFall
80 100
Fig. 11 Typical Pulse Width Distortion vs. Temperature
40
30
RL = 1 k
Vcc = 5.0 V
IF = 7.5 mA
20
10 RL = 350
0
-10
-60 -40 -20 0 20 40 60
TA - TEMPERATURE (˚C)
80 100
© 2003 Fairchild Semiconductor Corporation
Page 7 of 12
4/10/03

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관련 데이터시트

부품번호상세설명 및 기능제조사
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HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS

Fairchild Semiconductor
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