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PDF AR0132AT Data sheet ( Hoja de datos )
| Número de pieza | AR0132AT | |
| Descripción | 1/3-Inch CMOS Digital Image Sensor | |
| Fabricantes | Aptina Imaging Corporation | |
| Logotipo |  |
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Aptina Confidential and Proprietary
Preliminary‡
AR0132AT: 1/3-Inch CMOS Digital Image Sensor
Features
1/3-Inch CMOS Digital Image Sensor
AR0132AT Data Sheet
For the latest data sheet, refer to Aptina’s Web site: www.aptina.com
Features
• Superior low-light performance
• HD video (720p60)
• Linear or high dynamic range capture
• Video/Single Frame modes
• On-chip AE and statistics engine
• Parallel and serial output
• Auto black level calibration
• Context switching
• Temperature Sensor
Applications
• Video surveillance
• Automotive imaging
• 720p60 video applications
• High dynamic range imaging
General Description
Aptina's AR0132AT is a 1/3-inch CMOS digital image
sensor with an active-pixel array of 1280H x 960V. It
captures images in either linear or high dynamic range
modes, with a rolling-shutter readout. It includes
sophisticated camera functions such as auto exposure
control, windowing, and both video and single frame
modes. It is designed for both low light and high
dynamic range scene performance. It is programmable
through a simple two-wire serial interface. The
AR0132AT produces extraordinarily clear, sharp digital
pictures, and its ability to capture both continuous
video and single frames makes it the perfect choice for
a wide range of applications, including surveillance
and HD video.
Table 1:
Key Parameters
Parameter
Optical format
Active pixels
Pixel size
Color filter array
Shutter type
Input clock range
Typical Value
1/3-inch (6 mm)
1280 x 960 = 1.2 Mp
3.75μm
RGB Bayer, RCCC, or
monochrome
Electronic rolling shutter
6 – 50 MHz
Table 1:
Key Parameters (continued)
Parameter
Typical Value
Output clock maximum
Output Serial
Parallel
Frame
rate
Full resolution
720p
Responsivity
SNRMAX
Maximum dynamic range
Supply
voltage
I/O
Digital
Analog
HiSPi
Power consumption (typical)
Operating temperature
(ambient) -TA
Package options
74.25 MHz
HiSPi 12-, 14-, or 20-bit
12-bit
45 fps
60 fps
5.48 V/lux-sec
43.9 dB
>115 dB
1.8 or 2.8V*
1.8 V
2.8 V
0.4V or 1.8V
270mW (1280x720 60 fps
Parallel output Linear Mode)
460mW (1280x720 60 fps
Parallel output HiDy Mode)
–40°C to + 105° C (automotive)
9x9 mm iBGA
Bare die
Note: *1.8V VDD_IO is recommended for better row noise per-
formance
PDF: 2627625549 /Source: 9347974247
AR0132AT_DS Rev A Pub. 5/12 EN
1 Aptina reserves the right to change products or specifications without notice.
©2012 Aptina Imaging Corporation All rights reserved.
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Aptina without
notice. Products are only warranted by Aptina to meet Aptina’s production data sheet specifications.
1 page  
Aptina Confidential and Proprietary
AR0132AT: 1/3-Inch CMOS Digital Image Sensor
List of Figures
List of Figures
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Figure 35:
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Typical Configuration: Serial Four-Lane HiSPi Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Typical Configuration: Parallel Pixel Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
9 x 9 mm 64-Ball IBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Imaging a Scene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Spatial Illustration of Image Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Default Pixel Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
LV Format Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
HiSPi Transmitter and Receiver Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Line Timing and FRAME_VALID/LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
HDR Data Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
PLL-Generated Master Clock PLL Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Six Pixels in Normal and Column Mirror Readout Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Six Rows in Normal and Row Mirror Readout Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Frame Format with Embedded Data Lines Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Format of Embedded Statistics Output within a Frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Single READ from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Single READ from Current Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Sequential READ, Start from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Sequential READ, Start from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Single WRITE to Random Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Sequential WRITE, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Quantum Efficiency – Color Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Estimated Quantum Efficiency – Monochrome Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Two-Wire Serial Bus Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
I/O Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Differential Output Voltage for Clock or Data Pairs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Eye Diagram for Clock and Data Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Skew Within the PHY and Output Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Power Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
64-Ball iBGA Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
PDF: 2627625549 /Source: 9347974247
AR0132AT_DS Rev A Pub. 5/12 EN
5.
©2012 Aptina Imaging Corporation All rights reserved.
5 Page 
Aptina Confidential and Proprietary
AR0132AT: 1/3-Inch CMOS Digital Image Sensor
Functional Overview
Table 1:
Pin Descriptions, 9 x 9 mm, 64-ball iBGA
Name
SLVS0N
SLVS0P
SLVS1N
SLVS1P
STANDBY
VDD_PLL
SLVSCN
SLVSCP
SLVS2N
SLVS2P
VAA
EXTCLK
VDD_SLVS
SLVS3N
SLVS3P
DGND
VDD
AGND
SADDR
SCLK
SDATA
VAA_PIX
LINE_VALID
FRAME_VALID
PIXCLK
VDD_IO
DOUT8
DOUT9
DOUT10
DOUT11
TEST
DOUT4
DOUT5
DOUT6
DOUT7
TRIGGER
OE_BAR
DOUT0
DOUT1
DOUT2
DOUT3
RESET_BAR
FLASH
NC
Reserved
iBGA Pin
Type
A2 Output
A3 Output
A4 Output
A5 Output
A8 Input
B1 Power
B2 Output
B3 Output
B4 Output
B5 Output
B7, B8
Power
C1 Input
C2 Power
C3 Output
C4 Output
C5, D4, D5, E5, F5, G5, H5 Power
A6, A7, B6, C6, D6 Power
C7, C8
Power
D1 Input
D2 Input
D3 I/O
D7, D8
Power
E1 Output
E2 Output
E3 Output
E6, F6, G6, H6, H7 Power
F1 Output
F2 Output
F3 Output
F4 Output
F7 Input.
G1 Output
G2 Output
G3 Output
G4 Output
G7 Input
G8 Input
H1 Output
H2 Output
H3 Output
H4 Output
H8 Input
E4 Output
E7, E8
F8
Description
HiSPi serial data, lane 0, differential N.
HiSPi serial data, lane 0, differential P.
HiSPi serial data, lane 1, differential N.
HiSPi serial data, lane 1, differential P.
Standby-mode enable pin (active HIGH).
PLL power.
HiSPi serial DDR clock differential N.
HiSPi serial DDR clock differential P.
HiSPi serial data, lane 2, differential N.
HiSPi serial data, lane 2, differential P.
Analog power.
External input clock.
HiSPi power.
HiSPi serial data, lane 3, differential N.
HiSPi serial data, lane 3, differential P.
Digital ground.
Digital power.
Analog ground.
Two-Wire Serial address select.
Two-Wire Serial clock input.
Two-Wire Serial data I/O.
Pixel power.
Asserted when DOUT line data is valid.
Asserted when DOUT frame data is valid.
Pixel clock out. DOUT is valid on rising edge of this clock.
I/O supply power.
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output (MSB)
Manufacturing test enable pin (connect to DGND).
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output.
Exposure synchronization input.
Output enable (active LOW).
Parallel pixel data output (LSB)
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output.
Asynchronous reset (active LOW). All settings are restored to factory default.
Flash control output.
No connection.
No connection.
PDF: 2627625549 /Source: 9347974247
AR0132AT_DS Rev A Pub. 5/12 EN
11
.
©2012 Aptina Imaging Corporation All rights reserved.
11 Page | ||
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