PDF HCPL-0708500 Data sheet ( Hoja de datos )

Número de pieza	HCPL-0708500
Descripción	High Speed CMOS Optocoupler
Fabricantes	Agilent(Hewlett-Packard)
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No Preview Available ! Agilent HCPL-0708 High Speed CMOS Optocoupler Data Sheet Description Available in SO-8 package, the HCPL-0708 optocoupler utilizes the latest CMOS IC technology to achieve outstanding performance with very low power consumption. Basic building blocks of the HCPL- Functional Diagram NC 1 ANODE 2 8 VDD 7 NC 0708 are a high speed LED and a CMOS detector IC. The detector incorporates an integrated photodiode, a high-speed trans- impedance amplifier, and a voltage comparator with an output driver. Features • +5 V CMOS compatibility • 15 ns typical pulse width distortion • 30 ns max. pulse width distortion • 40 ns max. propagation delay skew • High speed: 15 MBd • 60 ns max. propagation delay • 10 kV/µs minimum common mode rejection • –40 to 100°C temperature range • Safety and regulatory approvals pending – UL recognized 2500 V rms for 1 min. per UL 1577 for HCPL-0708 – CSA component acceptance Notice #5 – VDE 0884 (TUV) approved for HCPL-0708 Option 060 CATHODE 3 NC 4 6 VO 5 GND TRUTH TABLE LED OFF ON VO, OUTPUT H L *A 0.1 µF bypass capacitor must be connected between pins 5 and 8. Applications • Scan drive in PDP • Digital field bus isolation: DeviceNet, SDS, Profibus • Multiplexed data transmission • Computer peripheral interface • Microprocessor system interface • DC/DC converter CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. 1 page Electrical Specifications Over recommended temperature (TA = –40°C to +100°C) and 4.5 V ≤ VDD ≤ 5.5 V. All typical specifications are at TA = 25°C, VDD = +5 V. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Notes Input Forward Voltage VF 1.3 1.5 1.8 V IF = 12 mA Input Reverse BVR 5 Breakdown Voltage V IR = 10 µA 1 Logic High Output Voltage VOH 4.0 4.8 V IF = 0, IO = –20 µA Logic Low Output Voltage VOL 0.01 0.1 V IF = 12 mA, IO = 20 µA Input Threshold Current Logic Low Output Supply Current ITH IDDL 8.2 mA IOL = 20 µA 6.0 14.0 mA IF = 12 mA 2 4 Logic High Output Supply Current IDDH 4.5 11.0 mA IF = 0 3 Switching Specifications Over recommended temperature (TA = –40°C to +100°C) and 4.5 V ≤ VDD ≤ 5.5 V. All typical specifications are at TA = 25°C, VDD = +5 V. Parameter Symbol Min. Typ. Max. Units Test Conditions Propagation Delay Time to Logic Low Output tPHL 20 35 60 ns IF = 12 mA, CL = 15 pF CMOS Signal Levels Propagation Delay Time to Logic High Output tPLH 13 21 60 ns IF = 12 mA, CL = 15 pF CMOS Signal Levels Pulse Width PW 100 ns Pulse Width Distortion \|PWD\| 0 14 30 ns IF = 12 mA, CL = 15 pF CMOS Signal Levels Propagation Delay Skew tPSK 40 ns IF = 12 mA, CL = 15 pF CMOS Signal Levels Output Rise Time (10 - 90%) tR 20 ns IF = 12 mA, CL = 15 pF CMOS Signal Levels Output Fall Time (90 - 10%) tF 25 ns IF = 12 mA, CL = 15 pF CMOS Signal Levels Common Mode Transient Immunity at Logic High Output \|CMH\| 10 15 kV/µs VCM = 1000 V, TA = 25°C, IF = 0 mA Common Mode Transient Immunity at Logic Low Output \|CML\| 10 15 kV/µs VCM = 1000 V, TA = 25°C, IF = 12 mA Fig. 5 5 2 3 4 5 Notes 1 1 2 3 4 5 5 5 Page

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