|
|
PDF AT25BCM512B Data sheet ( Hoja de datos )
| Número de pieza | AT25BCM512B | |
| Descripción | 512-Kilobit 2.7-volt Minimum SPI Serial Flash Memory | |
| Fabricantes | Adesto | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AT25BCM512B (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
Features
• Single 2.7V - 3.6V Supply
• Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
• 70 MHz Maximum Operating Frequency
– Clock-to-Output (tV) of 6 ns Maximum
• Flexible, Optimized Erase Architecture for Code + Data Storage Applications
– Uniform 4-Kbyte Block Erase
– Uniform 32-Kbyte Block Erase
– Full Chip Erase
• Hardware Controlled Locking of Protected Sectors via WP Pin
• 128-Byte Programmable OTP Security Register
• Flexible Programming
– Byte/Page Program (1 to 256 Bytes)
• Fast Program and Erase Times
– 2.5 ms Typical Page Program (256 Bytes) Time
– 100 ms Typical 4-Kbyte Block Erase Time
– 500 ms Typical 32-Kbyte Block Erase Time
• Automatic Checking and Reporting of Erase/Program Failures
• JEDEC Standard Manufacturer and Device ID Read Methodology
• Low Power Dissipation
– 6 mA Active Read Current (Typical at 20 MHz)
– 5 µA Deep Power-Down Current (Typical)
• Endurance: 100,000 Program/Erase Cycles
• Data Retention: 20 Years
• Complies with Full Industrial Temperature Range
• Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-pad Ultra Thin DFN (2 x 3 x 0.6 mm)
1. Description
The AT25BCM512B is a serial interface Flash memory device designed for use in a
wide variety of high-volume consumer based applications in which program code is
shadowed from Flash memory into embedded or external RAM for execution. The
flexible erase architecture of the AT25BCM512B, with its erase granularity as small as
4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional
data storage EEPROM devices.
The erase block sizes of the AT25BCM512B have been optimized to meet the needs
of today's code and data storage applications. By optimizing the size of the erase
blocks, the memory space can be used much more efficiently. Because certain code
modules and data storage segments must reside by themselves in their own erase
regions, the wasted and unused memory space that occurs with large sectored and
large block erase Flash memory devices can be greatly reduced. This increased
memory space efficiency allows additional code routines and data storage segments
to be added while still maintaining the same overall device density.
The device also contains a specialized OTP (One-Time Programmable) Security Reg-
ister that can be used for purposes such as unique device serialization, system-level
Electronic Serial Number (ESN) storage, locked key storage, etc.
Specifically designed for use in 3-volt systems, the AT25BCM512B supports read,
program, and erase operations with a supply voltage range of 2.7V to 3.6V. No sepa-
rate voltage is required for programming and erasing.
512-Kilobit
2.7-volt
Minimum
SPI Serial Flash
Memory
AT25BCM512B
Preliminary
3704BX–DFLASH–11/2012
1 page  
AT25BCM512B [Preliminary]
5. Device Operation
The AT25BCM512B is controlled by a set of instructions that are sent from a host controller,
commonly referred to as the SPI Master. The SPI Master communicates with the
AT25BCM512B via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial
Clock (SCK), Serial Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode
differing in respect to the SCK polarity and phase and how the polarity and phase control the
flow of data on the SPI bus. The AT25BCM512B supports the two most common modes, SPI
Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal
when in the inactive state (when the SPI Master is in standby mode and not transferring any
data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always
output on the falling edge of SCK.
Figure 5-1. SPI Mode 0 and 3
CS
SCK
SI MSB
LSB
SO
MSB
LSB
6. Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CS
pin has been asserted, the host controller must then clock out a valid 8-bit opcode on the SPI
bus. Following the opcode, instruction dependent information such as address and data bytes
would then be clocked out by the host controller. All opcode, address, and data bytes are trans-
ferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin.
Opcodes not supported by the AT25BCM512B will be ignored by the device and no operation
will be started. The device will continue to ignore any data presented on the SI pin until the start
of the next operation (CS pin being deasserted and then reasserted). In addition, if the CS pin is
deasserted before complete opcode and address information is sent to the device, then no oper-
ation will be performed and the device will simply return to the idle state and wait for the next
operation.
Addressing of the device requires a total of three bytes of information to be sent, representing
address bits A23-A0. Since the upper address limit of the AT25BCM512B memory array is
00FFFFh, address bits A23-A16 are always ignored by the device.
3704BX–DFLASH–11/2012
5
5 Page 
AT25BCM512B [Preliminary]
some point before the erase cycle completes, the WEL bit in the Status Register will be reset
back to the logical “0” state.
The device also incorporates an intelligent erase algorithm that can detect when a byte location
fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the Status
Register.
Figure 8-4. Chip Erase
CS
SCK
SI
SO
01234567
OPCODE
CCCCCCCC
MSB
HIGH-IMPEDANCE
9. Protection Commands and Features
9.1 Write Enable
The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Regis-
ter to a logical “1” state. The WEL bit must be set before a Byte/Page Program, erase, Program
OTP Security Register, or Write Status Register command can be executed. This makes the
issuance of these commands a two step process, thereby reducing the chances of a command
being accidentally or erroneously executed. If the WEL bit in the Status Register is not set prior
to the issuance of one of these commands, then the command will not be executed.
To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06h
must be clocked into the device. No address bytes need to be clocked into the device, and any
data clocked in after the opcode will be ignored. When the CS pin is deasserted, the WEL bit in
the Status Register will be set to a logical “1”. The complete opcode must be clocked into the
device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte
boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of
the WEL bit will not change.
Figure 9-1. Write Enable
CS
SCK
SI
SO
01234567
OPCODE
00000110
MSB
HIGH-IMPEDANCE
3704BX–DFLASH–11/2012
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT25BCM512B.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AT25BCM512B | 512-Kilobit 2.7-volt Minimum SPI Serial Flash Memory | Adesto |
| AT25BCM512C-MAHF-T | 512-Kilobit 2.7-volt Minimum SPI Serial Flash Memory | Adesto |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |