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부품번호 | AT25DF321A 기능 |
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기능 | 32-Mbit 2.7V Minimum Serial Peripheral Interface Serial Flash Memory | ||
제조업체 | Adesto | ||
로고 | |||
전체 30 페이지수
Features
• Single 2.7V - 3.6V Supply
• Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
– Supports RapidS Operation
– Supports Dual-Input Program and Dual-Output Read
• Very High Operating Frequencies
– 100MHz for RapidS
– 85MHz for SPI
– Clock-to-Output (tV) of 5ns Maximum
• Flexible, Optimized Erase Architecture for Code + Data Storage Applications
– Uniform 4-Kbyte Block Erase
– Uniform 32-Kbyte Block Erase
– Uniform 64-Kbyte Block Erase
– Full Chip Erase
• Individual Sector Protection with Global Protect/Unprotect Feature
– 64 Sectors of 64-Kbytes Each
• Hardware Controlled Locking of Protected Sectors via WP Pin
• Sector Lockdown
– Make Any Combination of 64-Kbyte Sectors Permanently Read-Only
• 128-Byte Programmable OTP Security Register
• Flexible Programming
– Byte/Page Program (1- to 256-Bytes)
• Fast Program and Erase Times
– 1.0ms Typical Page Program (256-Bytes) Time
– 50ms Typical 4-Kbyte Block Erase Time
– 250ms Typical 32-Kbyte Block Erase Time
– 400ms Typical 64-Kbyte Block Erase Time
• Program and Erase Suspend/Resume
• Automatic Checking and Reporting of Erase/Program Failures
• Software Controlled Reset
• JEDEC Standard Manufacturer and Device ID Read Methodology
• Low Power Dissipation
– 12mA Active Read Current (Typical at 20MHz)
– 5µA Deep Power-Down Current (Typical)
• Endurance: 100,000 Program/Erase Cycles
• Data Retention: 20 Years
• Complies with Full Industrial Temperature Range
• Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (208-mil wide)
– 8-pad Ultra Thin DFN (5 x 6 x 0.6mm)
– 9-ball UBGA (6 x 6 x 0.6 mm body - 1 mm pitch)
32-Mbit
2.7V Minimum
Serial Peripheral
Interface Serial
Flash Memory
AT25DF321A
3686F–DFLASH–1/2014
Figure 2-1.
CS 1
SO (SOI) 2
WP 3
GND 4
8-SOIC (Top View)
8 VCC
7 HOLD
6 SCK
5 SI (SIO)
Figure 2-2. 8-UDFN (Top View)
Figure 2-3. 9-UBGA (Top View)
CS 1
SO (SOI) 2
WP 3
GND 4
8 VCC
7 HOLD
6 SCK
5 SI (SIO)
SCK GND VCC
CS NC WP
SO SI HOLD
3. Block Diagram
Figure 3-1. Block Diagram
CS
SCK
SI (SIO)
SO (SOI)
WP
HOLD
INTERFACE
CONTROL
AND
LOGIC
CONTROL AND
PROTECTION LOGIC
Y-DECODER
X-DECODER
I/O BUFFERS
AND LATCHES
SRAM
DATA BUFFER
Y-GATING
FLASH
MEMORY
ARRAY
4. Memory Array
To provide the greatest flexibility, the memory array of the AT25DF321A can be erased in four levels of granularity including
a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which each sector can be
individually protected from program and erase operations. The size of the physical sectors is optimized for both code and data
storage applications, allowing both code and data segments to reside in their own isolated regions. The Memory Architecture
Diagram illustrates the breakdown of each erase level as well as the breakdown of each physical sector.
4 AT25DF321A
3686F–DFLASH–1/2014
4페이지 AT25DF321A
Table 6-1. Command Listing
Command
Read Commands
Read Array
Dual-Output Read Array
Program and Erase Commands
Block Erase (4-KBytes)
Block Erase (32-KBytes)
Block Erase (64-KBytes)
Chip Erase
Byte/Page Program (1- to 256-Bytes)
Dual-Input Byte/Page Program (1- to 256-Bytes)
Program/Erase Suspend
Program/Erase Resume
Protection Commands
Write Enable
Write Disable
Protect Sector
Unprotect Sector
Global Protect/Unprotect
Read Sector Protection Registers
Security Commands
Sector Lockdown
Freeze Sector Lockdown State
Read Sector Lockdown Registers
Program OTP Security Register
Read OTP Security Register
Status Register Commands
Read Status Register
Write Status Register Byte 1
Write Status Register Byte 2
Miscellaneous Commands
Reset
Read Manufacturer and Device ID
Deep Power-Down
Resume from Deep Power-Down
3686F–DFLASH–1/2014
Opcode
Clock
Frequency
Address
Bytes
Dummy
Bytes
Data
Bytes
1Bh 0001 1011 Up to 100MHz
0Bh 0000 1011
Up to 85MHz
03h 0000 0011
Up to 50MHz
3Bh 0011 1011
Up to 85MHz
3
3
3
3
2 1+
1 1+
0 1+
1 1+
20h 0010 0000 Up to 100MHz
52h 0101 0010 Up to 100MHz
D8h 1101 1000 Up to 100MHz
60h 0110 0000 Up to 100MHz
C7h 1100 0111 Up to 100MHz
02h 0000 0010 Up to 100MHz
A2h 1010 0010 Up to 100MHz
B0h 1011 0000 Up to 100MHz
D0h 1101 0000 Up to 100MHz
3
3
3
0
0
3
3
0
0
00
00
00
00
00
0 1+
0 1+
00
00
06h 0000 0110 Up to 100MHz
0
0
04h 0000 0100 Up to 100MHz
0
0
36h 0011 0110 Up to 100MHz
3
0
39h 0011 1001 Up to 100MHz
3
0
Use Write Status Register Byte 1 Command
3Ch 0011 1100 Up to 100MHz
3
0
0
0
0
0
1+
33h 0011 0011 Up to 100MHz
34h 0011 0100 Up to 100MHz
35h 0011 0101 Up to 100MHz
9Bh 1001 1011 Up to 100MHz
77h 0111 0111 Up to 100MHz
3
3
3
3
3
01
01
0 1+
0 1+
2 1+
05h 0000 0101 Up to 100MHz
01h 0000 0001 Up to 100MHz
31h 0011 0001 Up to 100MHz
0
0
0
0 1+
01
01
F0h 1111 0000
9Fh 1001 1111
B9h 1011 1001
ABh 1010 1011
Up to 100MHz
Up to 85MHz
Up to 100MHz
Up to 100MHz
0
0
0
0
01
0 1 to 4
00
00
7
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부품번호 | 상세설명 및 기능 | 제조사 |
AT25DF321 | 32M-Bit Serial Firmware Dataflash Memory | ATMEL Corporation |
AT25DF321 | (AT25DF321 / AT26DF321) 32M-Bit Serial Firmware Dataflash Memory | ATMEL Corporation |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |