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AT25DF512C-XMHNGU-T 데이터시트 PDF




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부품번호 AT25DF512C-XMHNGU-T 기능
기능 SPI Serial Flash Memory
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AT25DF512C-XMHNGU-T 데이터시트, 핀배열, 회로
AT25DF512C
512-Kbit, 1.65V Minimum
SPI Serial Flash Memory with Dual-I/O Support
Features
PRELIMINARY DATASHEET
Single 1.65V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual Output Read
85MHz Maximum Operating Frequency
Clock-to-Output (tV) of 6 ns
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 256-Byte Page erase
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Full Chip Erase
Hardware Controlled Locking of Protected Sectors via WP Pin
128-Byte Programmable OTP Security Register
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
1.5ms Typical Page Program (256 Bytes) Time
50ms Typical 4-Kbyte Block Erase Time
400ms Typical 32-Kbyte Block Erase Time
Automatic Checking and Reporting of Erase/Program Failures
Software Controlled Reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
200nA Ultra Deep Power Down current (Typical)
5µA Deep Power-Down Current (Typical)
25uA Standby current (Typical)
5mA Active Read Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Temperature Range:-10°C to +85°C (1.65V to 3.6V), -40°C to +85° (1.7V to 3.6V)
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil)
8-pad Ultra Thin DFN (2 x 3 x 0.6 mm)
8-lead TSSOP Package
DS-25DF512C–030A–4/2014




AT25DF512C-XMHNGU-T pdf, 반도체, 판매, 대치품
Figure 2-1. 8-SOIC Top View
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
Figure 2-2. 8-TSSOP Top View
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
Figure 2-3. 8-UDFN (Top View)
CS 1
SO 2
WP 3
GND 4
8 VCC
7 HOLD
6 SCK
5 SI
3. Block Diagram
Figure 3-1. Block Diagram
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AT25DF512C
DS-25DF512C–030A–4/2014
4

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AT25DF512C-XMHNGU-T 전자부품, 판매, 대치품
Table 6-1. Command Listing
Command
Chip Erase
Chip Erase (Legacy Command)
Byte/Page Program (1 to 256 Bytes)
Protection Commands
Write Enable
Write Disable
Security Commands
Program OTP Security Register
Read OTP Security Register
Status Register Commands
Read Status Register
Write Status Register Byte 1
Write Status Register Byte 2
Miscellaneous Commands
Reset
Read Manufacturer and Device ID
Read ID (Legacy Command)
Deep Power-Down
Resume from Deep Power-Down
Ultra Deep Power-Down
Opcode
60h 0110 0000
C7h 1100 0111
62h 0110 0010
02h 0000 0010
Clock
Frequency
Up to 85 MHz
Up to 85 MHz
Up to 85 MHz
Up to 85 MHz
Address
Bytes
0
0
0
3
Dummy
Bytes
0
0
0
0
Data
Bytes
0
0
0
1+
06h 0000 0110 Up to 85 MHz
0
0
0
04h 0000 0100 Up to 85 MHz
0
0
0
9Bh 1001 1011 Up to 85 MHz
77h 0111 0111 Up to 85 MHz
3
3
0 1+
2 1+
05h 0000 0101 Up to 85 MHz
01h 0000 0001 Up to 85 MHz
31h 0011 0001 Up to 85 MHz
0
0
0
0 1+
01
01
F0h 1111 0000 Up to 85 MHz
9Fh 1001 1111 Up to 85 MHz
15h 0001 0101 Up to 85 MHz
B9h 1011 1001 Up to 85 MHz
ABh 1010 1011 Up to 85 MHz
79h 0111 1001 Up to 85 MHz
0
0
0
0
0
0
0 1(D0h)
0 1 to 4
02
00
00
00
1. Varies by voltage range. See Table 13.4 “AC Characteristics - Maximum Clock Frequencies”.
7. Read Commands
7.1 Read Array
The Read Array command can be used to sequentially read a continuous stream of data from the device by simply
providing the clock signal once the initial starting address is specified. The device incorporates an internal address
counter that automatically increments every clock cycle.
Two opcodes (0Bh and 03h) can be used for the Read Array command. The use of each opcode depends on the
maximum clock frequency that will be used to read data from the device. The 0Bh opcode can be used at any clock
frequency up to the maximum specified by fCLK, and the 03h opcode can be used for lower frequency read operations up
to the maximum specified by fRDLF.
AT25DF512C
DS-25DF512C–030A–4/2014
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