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PDF AT25DF512C-MAHNGU-T Data sheet ( Hoja de datos )
| Número de pieza | AT25DF512C-MAHNGU-T | |
| Descripción | SPI Serial Flash Memory | |
| Fabricantes | Adesto | |
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AT25DF512C
512-Kbit, 1.65V Minimum
SPI Serial Flash Memory with Dual-I/O Support
Features
PRELIMINARY DATASHEET
Single 1.65V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual Output Read
85MHz Maximum Operating Frequency
Clock-to-Output (tV) of 6 ns
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 256-Byte Page erase
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Full Chip Erase
Hardware Controlled Locking of Protected Sectors via WP Pin
128-Byte Programmable OTP Security Register
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
1.5ms Typical Page Program (256 Bytes) Time
50ms Typical 4-Kbyte Block Erase Time
400ms Typical 32-Kbyte Block Erase Time
Automatic Checking and Reporting of Erase/Program Failures
Software Controlled Reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
200nA Ultra Deep Power Down current (Typical)
5µA Deep Power-Down Current (Typical)
25uA Standby current (Typical)
5mA Active Read Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Temperature Range:-10°C to +85°C (1.65V to 3.6V), -40°C to +85° (1.7V to 3.6V)
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil)
8-pad Ultra Thin DFN (2 x 3 x 0.6 mm)
8-lead TSSOP Package
DS-25DF512C–030A–4/2014
1 page  
4. Memory Array
To provide the greatest flexibility, the memory array of the AT25DF512C can be erased in three levels of granularity
including a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing
both code and data segments to reside in their own erase regions. The Memory Architecture Diagram illustrates the
breakdown of each erase level.
Figure 4-1. Memory Architecture Diagram
Block Erase Detail
32KB
4KB
Block Erase
Block Erase
(52h Command) (20h Command)
Block Address
Range
32KB
32KB
4KB 00FFFFh – 00F000h
4KB 00EFFFh – 00E000h
4KB 00DFFFh – 00D000h
4KB 00CFFFh – 00C000h
4KB 00BFFFh – 00B000h
4KB 00AFFFh – 00A000h
4KB 009FFFh – 009000h
4KB 008FFFh – 008000h
4KB 007FFFh – 007000h
4KB 006FFFh – 006000h
4KB 005FFFh – 005000h
4KB 004FFFh – 004000h
4KB 003FFFh – 003000h
4KB 002FFFh – 002000h
4KB 001FFFh – 001000h
4KB 000FFFh – 000000h
Page Program Detail
1-256 Byte
Page Program
(02h Command)
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
Page Address
Range
00FFFFh – 00FF00h
00FEFFh – 00FE00h
00FDFFh – 00FD00h
00FCFFh – 00FC00h
00FBFFh – 00FB00h
00FAFFh – 00FA00h
00F9FFh – 00F900h
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
0006FFh – 000600h
0005FFh – 000500h
0004FFh – 000400h
0003FFh – 000300h
0002FFh – 000200h
0001FFh – 000100h
0000FFh – 000000h
5. Device Operation
The AT25DF512C is controlled by a set of instructions that are sent from a host controller, commonly referred to as the
SPI Master. The SPI Master communicates with the AT25DF512C via the SPI bus which is comprised of four signal lines:
Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the
SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25DF512C
supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the
polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any
data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge
of SCK.
AT25DF512C
DS-25DF512C–030A–4/2014
5
5 Page 
8.3 Block Erase
A block of 4 or 32 Kbytes can be erased (all bits set to the logical “1” state) in a single operation by using one of three
different opcodes for the Block Erase command. An opcode of 20h is used for a 4-Kbyte erase, and an opcode of 52h or
D8h is used for a 32-Kbyte erase. Before a Block Erase command can be started, the Write Enable command must have
been previously issued to the device to set the WEL bit of the Status Register to a logical “1” state.
To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must be
clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address within the
4- or 32-Kbyte block to be erased must be clocked in. Any additional data clocked into the device will be ignored. When
the CS pin is deasserted, the device will erase the appropriate block. The erasing of the block is internally self-timed and
should take place in a time of tBLKE.
Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded by the
device. Therefore, for a 4-Kbyte erase, address bits A11-A0 will be ignored by the device and their values can be either a
logical “1” or “0”. For a 32-Kbyte erase, address bits A14-A0 will be ignored by the device. Despite the lower order
address bits not being decoded by the device, the complete three address bytes must still be clocked into the device
before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits);
otherwise, the device will abort the operation and no erase operation will be performed.
If the memory is in the protected state, then the Block Erase command will not be executed, and the device will return to
the idle state once the CS pin has been deasserted.
The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle aborts due to an incomplete
address being sent, the CS pin being deasserted on uneven byte boundaries, or because a memory location within the
region to be erased is protected.
While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device
is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tBLKE time to
determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status
Register will be reset back to the logical “0” state.
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If
an erase error occurs, it will be indicated by the EPE bit in the Status Register.
Figure 8-3. Block Erase
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12
26 27 28 29 30 31
OPCODE
ADDRESS BITS A23-A0
CCCCCCCCAAAAAA
MSB
MSB
AAAAAA
HIGH-IMPEDANCE
8.4 Chip Erase
The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip Erase
command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit
of the Status Register to a logical “1” state.
Three opcodes (60h, 62h, and C7h) can be used for the Chip Erase command. There is no difference in device
functionality when utilizing the three opcodes, so they can be used interchangeably. To perform a Chip Erase, one of the
three opcodes must be clocked into the device. Since the entire memory array is to be erased, no address bytes need to
be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the
AT25DF512C
DS-25DF512C–030A–4/2014
11
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