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AT25DF641A-MH-Y 데이터시트 PDF




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부품번호 AT25DF641A-MH-Y 기능
기능 2.7V Minimum SPI Serial Flash Memory
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AT25DF641A-MH-Y 데이터시트, 핀배열, 회로
AT25DF641A
64-Mbit, 2.7V Minimum SPI Serial Flash Memory
with Dual–I/O Support
Features
DATASHEET
Single 2.7V - 3.6V supply
Serial Peripheral Interface (SPI) compatible
Supports SPI Modes 0 and 3
Supports RapidSoperation
Supports Dual-Input Program and Dual-Output Read
Very high operating frequencies
100MHz for RapidS
85MHz for SPI
Clock-to-output time (tV) of 5ns maximum
Flexible, optimized erase architecture for code + data storage applications
Uniform 4KB, 32KB, and 64KB Block Erase
Full Chip Erase
Individual sector protection with Global Protect/Unprotect feature
128 Sectors of 64KB each
Hardware controlled locking of protected sectors via WP pin
Sector Lockdown
Make any combination of 64KB sectors permanently read-only
128-byte One-Time Programmable (OTP) Security Register
64 bytes factory preprogrammed
64 bytes user programmable
Flexible programming
Byte/Page Program (1 to 256 bytes)
Fast program and erase times
2.5ms typical Page Program (256 bytes) time
75ms typical 4KB Block Erase time
300ms typical 32KB Block Erase time
600ms typical 64KB Block Erase time
Program and Erase Suspend/Resume
Automatic checking and reporting of erase/program failures
Software controlled reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low power dissipation
25mA Active Read current (typical at 20MHz)
5μA Deep Power-Down current (typical)
Endurance: 100,000 program/erase cycles
Data retention: 20 years
Complies with full industrial temperature range
Industry standard green (Pb/Halide-free/RoHS compliant) package options
8-lead SOIC (0.208” wide)
8-pad Ultra-thin DFN (5 x 6 x 0.6mm)
8793D–DFLASH–5/2013




AT25DF641A-MH-Y pdf, 반도체, 판매, 대치품
Table 2-1. Pin Descriptions (Continued)
Symbol
HOLD
VCC
GND
Name and Function
Hold: The HOLD pin is used to temporarily pause serial communication without
deselecting or resetting the device. While the HOLD pin is asserted, transitions on
the SCK pin and data on the SI pin will be ignored, and the SO pin will be in a
high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for
a Hold condition to start. A Hold condition pauses serial communication only and
does not have an effect on internally self-timed operations such as a program or
erase cycle. See “Hold” on page 46 for additional details on the Hold operation.
The HOLD pin is internally pulled-high and may be left floating if the Hold function
will not be used. However, it is recommended that the HOLD pin also be externally
connected to VCC whenever possible.
Device Power Supply: The VCC pin is used to supply the source voltage to the
device.
Operations at invalid VCC voltages may produce spurious results and should not be
attempted.
Ground: The ground reference for the power supply. GND should be connected to
the system ground.
Asserted
State
Low
Type
Input
Power
Power
Figure 2-1. Pinouts
8-lead SOIC
(Top View)
CS
SO (SOI)
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI (SIO)
8-pad UDFN
(Top View)
CS 1
SO (SOI) 2
WP 3
GND 4
8 VCC
7 HOLD
6 SCK
5 SI (SIO)
AT25DF641A [DATASHEET]
8793D–DFLASH–5/2013
4

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AT25DF641A-MH-Y 전자부품, 판매, 대치품
5. Device Operation
The AT25DF641A is controlled by a set of instructions that are sent from a host controller, commonly referred to as the
SPI master. The SPI master communicates with the AT25DF641A via the SPI bus which is comprised of four signal lines:
Chip Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
The AT25DF641A features a Dual-Input Program mode in which the SO pin becomes an input. Similarly, the device also
features a Dual-Output Read mode in which the SI pin becomes an output. In the Dual-Input Byte/Page Program
command description, the SO pin will be referred to as the SOI (Serial Output/Input) pin, and in the Dual-Output Read
Array command, the SI pin will be referenced as the SIO (Serial Input/Output) pin.
The SPI protocol defines a total of four modes of operation (Mode 0, 1, 2, or 3) with each mode differing in respect to the
SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25DF641A
supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the
polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any
data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge
of SCK.
Figure 5-1. SPI Mode 0 and 3
CS
SCK
SI MSB
LSB
SO
MSB
LSB
6. Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted,
the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction-dependent
information, such as address and data bytes, would then be clocked out by the host controller. All opcode, address, and
data bytes are transferred with the Most-Significant Bit (MSB) first. An operation is ended by deasserting the CS pin.
Opcodes not supported by the AT25DF641A will be ignored by the device and no operation will be started. The device
will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and
then reasserted). In addition, if the CS pin is deasserted before complete opcode and address information is sent to the
device, then no operation will be performed, and the device will simply return to the idle state and wait for the next
operation.
Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0.
Since the upper address limit of the AT25DF641A memory array is 7FFFFFh, address bit A23 is always ignored by the
device.
AT25DF641A [DATASHEET]
8793D–DFLASH–5/2013
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