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AT25DN256-XMHFGP-B 데이터시트 PDF




Adesto에서 제조한 전자 부품 AT25DN256-XMHFGP-B은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 AT25DN256-XMHFGP-B 기능
기능 2.3V Minimum SPI Serial Flash Memory
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AT25DN256-XMHFGP-B 데이터시트, 핀배열, 회로
AT25DN256
256-Kbit, 2.3V Minimum
SPI Serial Flash Memory with Dual-Read Support
Features
PRELIMINARY DATASHEET
Single 2.3V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual Output Read
104MHz Maximum Operating Frequency
Clock-to-Output (tV) of 6ns
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 256-Byte Page erase
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Full Chip Erase
Hardware Controlled Locking of Protected Sectors via WP Pin
128-Byte Programmable OTP Security Register
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
1.5ms Typical Page Program (256 Bytes) Time
40ms Typical 4-Kbyte Block Erase Time
320ms Typical 32-Kbyte Block Erase Time
Automatic Checking and Reporting of Erase/Program Failures
Software Controlled Reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
350nA Ultra Deep Power Down current (Typical)
5µA Deep Power-Down Current (Typical)
25uA Standby current (Typical)
6mA Active Read Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil)
8-pad Ultra Thin DFN (2 x 3 x 0.6mm)
8-lead TSSOP Package
DS-25DN256–039B–5/2014




AT25DN256-XMHFGP-B pdf, 반도체, 판매, 대치품
3. Block Diagram
Figure 3-1. Block Diagram
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AT25DN256
DS-25DN256–039B–5/2014
4

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AT25DN256-XMHFGP-B 전자부품, 판매, 대치품
Table 6-1. Command Listing
Command
Write Status Register Byte 2
Miscellaneous Commands
Reset
Read Manufacturer and Device ID
Read ID (Legacy Command)
Deep Power-Down
Resume from Deep Power-Down
Ultra Deep Power-Down
Opcode
31h 0011 0001
Clock
Frequency
Up to 104MHz
Address
Bytes
0
Dummy
Bytes
0
Data
Bytes
1
F0h 1111 0000 Up to 104MHz
9Fh 1001 1111 Up to 104MHz
15h 0001 0101 Up to 104MHz
B9h 1011 1001 Up to 104MHz
ABh 1010 1011 Up to 104MHz
79h 0111 1001 Up to 104MHz
0
0
0
0
0
0
0 1 (D0h)
0 1 to 4
02
00
00
00
7. Read Commands
7.1 Read Array
The Read Array command can be used to sequentially read a continuous stream of data from the device by simply
providing the clock signal once the initial starting address is specified. The device incorporates an internal address
counter that automatically increments every clock cycle.
Two opcodes (0Bh and 03h) can be used for the Read Array command. The use of each opcode depends on the
maximum clock frequency that will be used to read data from the device. The 0Bh opcode can be used at any clock
frequency up to the maximum specified by fCLK, and the 03h opcode can be used for lower frequency read operations up
to the maximum specified by fRDLF.
To perform the Read Array operation, the CS pin must first be asserted and the appropriate opcode (0Bh or 03h) must be
clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the
starting address location of the first byte to read within the memory array. Following the three address bytes, an
additional dummy byte needs to be clocked into the device if the 0Bh opcode is used for the Read Array operation.
After the three address bytes (and the dummy byte if using opcode 0Bh) have been clocked in, additional clock cycles
will result in data being output on the SO pin. The data is always output with the MSB of a byte first. When the last byte
(00FFFFh) of the memory array has been read, the device will continue reading back at the beginning of the array
(000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array.
Deasserting the CS pin will terminate the read operation and put the SO pin into high-impedance state. The CS pin can
be deasserted at any time and does not require a full byte of data be read.
Figure 7-1. Read Array - 03h Opcode
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12
29 30 31 32 33 34 35 36 37 38 39 40
OPCODE
ADDRESS BITS A23-A0
0 0 0 0 0 0 1 1AAAAAA
MSB
MSB
HIGH-IMPEDANCE
AAA
DATA BYTE 1
DDDDDDDDDD
MSB
MSB
AT25DN256
DS-25DN256–039B–5/2014
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