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AT25SF081-SHD-T 데이터시트 PDF




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기능 2.5V Minimum SPI Serial Flash Memory
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AT25SF081-SHD-T 데이터시트, 핀배열, 회로
AT25SF081
8-Mbit, 2.5V Minimum
SPI Serial Flash Memory with Dual-I/O and Quad-IO Support
Features
PRELIMINARY DATASHEET
Single 2.5V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual and Quad Output Read
104MHz Maximum Operating Frequency
Clock-to-Output (tV) of 6 ns
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Uniform 64-Kbyte Block Erase
Full Chip Erase
Hardware Controlled Locking of Protected Blocks via WP Pin
3 Protected Programmable Security Register Pages
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
0.7ms Typical Page Program (256 Bytes) Time
70ms Typical 4-Kbyte Block Erase Time
300ms Typical 32-Kbyte Block Erase Time
600ms Typical 64-Kbyte Block Erase Time
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
2µA Deep Power-Down Current (Typical)
10µA Standby current (Typical)
4mA Active Read Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil and 208-mil)
8-pad Ultra Thin DFN (5 x 6 x 0.6 mm and 2 x 3 x 0.6 mm) (1)
8-lead TSSOP (4 x 4 mm)(1)
1. TSSOP and DFN packages are not currently in production. Package outline dimensions are subject
to change.
DS-25SF081A–045B–5/2014




AT25SF081-SHD-T pdf, 반도체, 판매, 대치품
Figure 1-1. 8-SOIC, 8-TSSOP (Top View)
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
2. Block Diagram
Figure 2-1. Block Diagram
Figure 1-2. 8-UDFN (Top View)
CS 1
SO 2
WP 3
GND 4
8 VCC
7 HOLD
6 SCK
5 SI
Control and
CS Protection Logic
SCK
SI (I/O0)
SO (I/O1)
Interface
Control
And
Logic
Y-Decoder
WP (I/O2)
HOLD (I/O3)
X-Decoder
Note: I/O3-0 pin naming convention is used for Dual-I/O and Quad-I/O commands.
I/O Buffers
and Latches
SRAM
Data Buffer
Y-Gating
Flash
Memory
Array
3. Memory Array
To provide the greatest flexibility, the memory array of the AT25SF081 can be erased in four levels of granularity
including a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing
both code and data segments to reside in their own erase regions. The Memory Architecture Diagram illustrates the
breakdown of each erase level.
AT25SF081
DS-25SF081A–045B–5/2014
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AT25SF081-SHD-T 전자부품, 판매, 대치품
Table 5-1. Command Listing
Command
Read Commands
Read Array
Dual Output Read
Dual I/O Read
Quad Output Read
Quad I/O Read
Continuous Read Mode Reset - Dual
Continuous Read Mode Reset - Quad
Program and Erase Commands
Block Erase (4 Kbytes)
Block Erase (32 Kbytes)
Block Erase (64 Kbytes)
Chip Erase
Byte/Page Program (1 to 256 Bytes)
Protection Commands
Write Enable
Write Disable
Security Commands
Erase Security Register Page
Program Security Register Page
Read Security Register Page
Status Register Commands
Read Status Register Byte 1
Read Status Register Byte 2
Write Status Register
Write Enable for Volatile Status
Register
Miscellaneous Commands
Read Manufacturer and Device ID
Read ID
Opcode
0Bh
03h
3Bh
BBh
6Bh
EBh
FFFFh
FFh
0000 1011
0000 0011
0011 1011
1011 1011
0110 1011
1110 1011
1111 1111
1111 1111
1111 1111
20h 0010 0000
52h 0101 0010
D8h 1101 1000
60h 0110 0000
C7h 1100 0111
02h 0000 0010
06h 0000 0110
04h 0000 0100
44h 0100 0100
42h 0100 0010
48h 0100 1000
05h 0000 0101
35h 0011 0101
01h 0000 0001
50h 0101 0000
9Fh 1001 1111
90h 1001 0000
Clock
Frequency
Address Dummy Data Section
Bytes Bytes Bytes Link
Up to 85 MHz
Up to 50 MHz
Up to 85 MHz
Up to 85 MHz
Up to 85 MHz
Up to 85 MHz
Up to 104 MHz
Up to 104 MHz
3
3
3
3
3
3
0
0
1 1+
6.1
0 1+
1 1+ 6.2
0 1+ 6.3
1 1+ 6.4
1 1+ 6.5
0 0 6.6
0 0 6.6
Up to 104 MHz
Up to 104 MHz
Up to 104MHz
Up to 104 MHz
Up to 104 MHz
Up to 104 MHz
3
3
3
0
0
3
00
0 0 7.2
00
00
7.3
00
0 1+ 7.1
Up to 104 MHz
Up to 104 MHz
0
0
0 0 8.1
0 0 8.2
Up to 104 MHz
Up to 104 MHz
Up to 85MHz
3
3
3
0 0 9.1
0 1+ 9.2
1 1+ 9.3
Up to 104 MHz
Up to 104 MHz
Up to 104 MHz
Up to 104MHz
0
0
0
0
01
10.1
01
0
1 or 2
10.2
0 0 10.3
Up to 104MHz
Up to 104 MHz
0
3
0 3 11.1
0 2 11.2
AT25SF081
DS-25SF081A–045B–5/2014
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