PDF AT25SF081-SSHD-T Data sheet ( Hoja de datos )

Número de pieza	AT25SF081-SSHD-T
Descripción	2.5V Minimum SPI Serial Flash Memory
Fabricantes	Adesto
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AT25SF081 8-Mbit, 2.5V Minimum SPI Serial Flash Memory with Dual-I/O and Quad-IO Support Features PRELIMINARY DATASHEET  Single 2.5V - 3.6V Supply  Serial Peripheral Interface (SPI) Compatible  Supports SPI Modes 0 and 3  Supports Dual and Quad Output Read  104MHz Maximum Operating Frequency  Clock-to-Output (tV) of 6 ns  Flexible, Optimized Erase Architecture for Code + Data Storage Applications  Uniform 4-Kbyte Block Erase  Uniform 32-Kbyte Block Erase  Uniform 64-Kbyte Block Erase  Full Chip Erase  Hardware Controlled Locking of Protected Blocks via WP Pin  3 Protected Programmable Security Register Pages  Flexible Programming  Byte/Page Program (1 to 256 Bytes)  Fast Program and Erase Times  0.7ms Typical Page Program (256 Bytes) Time  70ms Typical 4-Kbyte Block Erase Time  300ms Typical 32-Kbyte Block Erase Time  600ms Typical 64-Kbyte Block Erase Time  JEDEC Standard Manufacturer and Device ID Read Methodology  Low Power Dissipation  2µA Deep Power-Down Current (Typical)  10µA Standby current (Typical)  4mA Active Read Current (Typical)  Endurance: 100,000 Program/Erase Cycles  Data Retention: 20 Years  Complies with Full Industrial Temperature Range  Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options  8-lead SOIC (150-mil and 208-mil)  8-pad Ultra Thin DFN (5 x 6 x 0.6 mm and 2 x 3 x 0.6 mm) (1)  8-lead TSSOP (4 x 4 mm)(1) 1. TSSOP and DFN packages are not currently in production. Package outline dimensions are subject  to change. DS-25SF081A–045B–5/2014 1 page Figure 3-1. Memory Architecture Diagram Block Erase Detail 64KB 32KB 4KB 64KB 32KB 32KB 64KB 32KB 32KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB 4KB Block Address Range 0FFFFFh – 0FF000h 0FEFFFh – 0FE000h 0FDFFFh – 0FD000h 0FCFFFh – 0FC000h 0FBFFFh – 0FB000h 0FAFFFh – 0FA000h 0F9FFFh – 0F9000h 0F8FFFh – 0F8000h 0F7FFFh – 0F7000h 0F6FFFh – 0F6000h 0F5FFFh – 0F5000h 0F4FFFh – 0F4000h 0F3FFFh – 0F3000h 0F2FFFh – 0F2000h 0F1FFFh – 0F1000h 0F0FFFh – 0F0000h 0EFFFFh – 0EF000h 0EEFFFh – 0EE000h 0EDFFFh – 0ED000h 0ECFFFh – 0EC000h 0EBFFFh – 0EB000h 0EAFFFh – 0EA000h 0E9FFFh – 0E9000h 0E8FFFh – 0E8000h 0E7FFFh – 0E7000h 0E6FFFh – 0E6000h 0E5FFFh – 0E5000h 0E4FFFh – 0E4000h 0E3FFFh – 0E3000h 0E2FFFh – 0E2000h 0E1FFFh – 0E1000h 0E0FFFh – 0E0000h 64KB 32KB 32KB 4KB 00FFFFh – 00F000h 4KB 00EFFFh – 00E000h 4KB 00DFFFh – 00D000h 4KB 00CFFFh – 00C000h 4KB 00BFFFh – 00B000h 4KB 00AFFFh – 00A000h 4KB 009FFFh – 009000h 4KB 008FFFh – 008000h 4KB 007FFFh – 007000h 4KB 006FFFh – 006000h 4KB 005FFFh – 005000h 4KB 004FFFh – 004000h 4KB 003FFFh – 003000h 4KB 002FFFh – 002000h 4KB 001FFFh – 001000h 4KB 000FFFh – 000000h Page Program Detail 1-256 Byte 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes Page Address Range 0FFFFFh – 0FFF00h 0FFEFFh – 0FFE00h 0FFDFFh – 0FFD00h 0FFCFFh – 0FFC00h 0FFBFFh – 0FFB00h 0FFAFFh – 0FFA00h 0FF9FFh – 0FF900h 0FF8FFh – 0FF800h 0FF7FFh – 0FF700h 0FF6FFh – 0FF600h 0FF5FFh – 0FF500h 0FF4FFh – 0FF400h 0FF3FFh – 0FF300h 0FF2FFh – 0FF200h 0FF1FFh – 0FF100h 0FF0FFh – 0FF000h 0FEFFFh – 0FEF00h 0FEEFFh – 0FEE00h 0FEDFFh – 0FED00h 0FECFFh – 0FEC00h 0FEBFFh – 0FEB00h 0FEAFFh – 0FEA00h 0FE9FFh – 0FE900h 0FE8FFh – 0FE800h 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 0017FFh – 001700h 0016FFh – 001600h 0015FFh – 001500h 0014FFh – 001400h 0013FFh – 001300h 0012FFh – 001200h 0011FFh – 001100h 0010FFh – 001000h 000FFFh – 000F00h 000EFFh – 000E00h 000DFFh – 000D00h 000CFFh – 000C00h 000BFFh – 000B00h 000AFFh – 000A00h 0009FFh – 000900h 0008FFh – 000800h 0007FFh – 000700h 0006FFh – 000600h 0005FFh – 000500h 0004FFh – 000400h 0003FFh – 000300h 0002FFh – 000200h 0001FFh – 000100h 0000FFh – 000000h AT25SF081 DS-25SF081A–045B–5/2014 5 5 Page Figure 6-5. Dual-I/O Read Array (Previous command set M5, M4 = 1,0) CS SCK I/O0 (SI) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Address Bits A23-A16 Address Bits A15-A8 A7-A0 M7-M0 Byte 1 Byte 2 A22 A20 A18 A16 A14 A MSB A0 M6 M4 M2 M0 D6 D4 D2 D0 D6 I/O1 (SO) A23 A21 A19 A17 A15 A MSB A1 M7 M5 M3 M1 D7 D5 D3 D1 D7 6.4 Quad-Output Read Array (6Bh) The Quad-Output Read Array command is similar to the Dual-Output Read Array command. The Quad-Output Read Array command allows four bits of data to be clocked out of the device on every clock cycle, rather than just one or two. The Quad Enable bit (QE) of the Status Register must be set to enable for the Quad-Output Read Array instruction. The Quad-Output Read Array command can be used at any clock frequency, up to the maximum specified by fRDQO. To perform the Quad-Output Read Array operation, the CS pin must first be asserted and then the opcode 6Bh must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the location of the first byte to read within the memory array. Following the three address bytes, a single dummy byte must also be clocked into the device. After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being output on the I/O3-0 pins. The data is always output with the MSB of a byte first and the MSB is always output on the I/O3 pin. During the first clock cycle, bit 7 of the first data byte will be output on the I/O3 pin while bits 6, 5, and 4 of the same data byte will be output on the I/O2, I/O1, and I/O0 pins, respectively. During the next clock cycle, bits 3, 2, 1, and 0 of the first data byte will be output on the I/O3, I/O2, I/O1 and I/O0 pins, respectively. The sequence continues with each byte of data being output after every two clock cycles. When the last byte (0FFFFFh) of the memory array has been read, the device will continue reading from the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array.Deasserting the CS pin will terminate the read operation and put the WP, HOLD, SO, SI pins into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read. AT25SF081 DS-25SF081A–045B–5/2014 11 11 Page

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