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AT45DB011D-SH-SL955 데이터시트 PDF




Adesto에서 제조한 전자 부품 AT45DB011D-SH-SL955은 전자 산업 및 응용 분야에서
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기능 1-megabit 2.7-volt Minimum DataFlash
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AT45DB011D-SH-SL955 데이터시트, 핀배열, 회로
Features
Single 2.7V to 3.6V Supply
RapidSSerial Interface: 66MHz Maximum Clock Frequency
– SPI Compatible Modes 0 and 3
User Configurable Page Size
– 256-Bytes per Page
– 264-Bytes per Page
– Page Size Can Be Factory Pre-configured for 256-Bytes
Page Program Operation
– Intelligent Programming Operation
– 512-Pages (256-/264-Bytes/Page) Main Memory
Flexible Erase Options
– Page Erase (256-Bytes)
– Block Erase (2-Kbytes)
– Sector Erase (32-Kbytes)
– Chip Erase (1Mbits)
One SRAM Data Buffer (256-/264-Bytes)
Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
Low-power Dissipation
– 7mA Active Read Current Typical
– 25µA Standby Current Typical
– 15µA Deep Power-down Typical
Hardware and Software Data Protection Features
– Individual Sector
Sector Lockdown for Secure Code and Data Storage
– Individual Sector
Security: 128-byte Security Register
– 64-byte User Programmable Space
– Unique 64-byte Device Identifier
JEDEC Standard Manufacturer and Device ID Read
100,000 Program/Erase Cycles Per Page Minimum
Data Retention – 20 Years
Industrial Temperature Range
Green (Pb/Halide-free/RoHS Compliant) Packaging Options
1-megabit
2.7-volt
Minimum
DataFlash®
AT45DB011D
1. Description
The Adesto® AT45DB011D is a 2.7V, serial-interface Flash memory ideally suited for
a wide variety of digital voice-, image-, program code- and data-storage applications.
The AT45DB011D supports RapidS serial interface for applications requiring very
high speed operations. RapidS serial interface is SPI compatible for frequencies up to
66MHz. Its 1,081,344-bits of memory are organized as 512 pages of 256-bytes or
264-bytes each. In addition to the main memory, the AT45DB011D also contains one
SRAM buffer of 256-/264-bytes. EEPROM emulation (bit or byte alterability) is easily
handled with a self-contained three step read-modify-write operation. Unlike conven-
tional Flash memories that are accessed randomly with multiple address lines and a
parallel interface, the Adesto DataFlash® uses a RapidS serial interface to sequen-
tially access its data. The simple sequential access dramatically reduces active pin
count, facilitates hardware layout, increases system reliability, minimizes switching
noise, and reduces package size.
3639K–DFLASH–6/2014




AT45DB011D-SH-SL955 pdf, 반도체, 판매, 대치품
4. Memory Array
To provide optimal flexibility, the memory array of the AT45DB011D is divided into three levels of
granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illus-
trates the breakdown of each level and details the number of pages per sector and block. All
program operations to the DataFlash occur on a page-by-page basis. The erase operations can
be performed at the chip, sector, block or page level.
Figure 4-1. Memory Architecture Diagram
SECTOR ARCHITECTURE
SECTOR 0a = 8 Pages
2,048-/2,112-bytes
SECTOR 0a
BLOCK ARCHITECTURE
BLOCK 0
BLOCK 1
BLOCK 2
8 Pages
PAGE ARCHITECTURE
PAGE 0
PAGE 1
SECTOR 0b = 120 Pages
31,744-/32,726-bytes
SECTOR 1 = 128 Pages
32,768-/33,792-bytes
SECTOR 2 = 128 Pages
32,768-/33,792-bytes
BLOCK 14
BLOCK 15
BLOCK 16
BLOCK 17
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
SECTOR 3 = 128 Pages
32,768-/33,792-bytes
BLOCK 62
BLOCK 63
Block = 2,048-/2,112-bytes
PAGE 510
PAGE 511
Page = 256-/264-bytes
5. Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions
and their associated opcodes are contained in Tables 15-1 through 15-7. A valid instruction
starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer
or main memory address location. While the CS pin is low, toggling the SCK pin controls the
loading of the opcode and the desired buffer or main memory address location through the SI
(serial input) pin. All instructions, addresses, and data are transferred with the most significant
bit (MSB) first.
Buffer addressing for the DataFlash standard page size (264-bytes) is referenced in the data-
sheet using the terminology BFA8 - BFA0 to denote the nine address bits required to designate
a byte address within a buffer. Main memory addressing is referenced using the terminology
PA8 - PA0 and BA8 - BA0, where PA8 - PA0 denotes the nine address bits required to designate
a page address and BA8 - BA0 denotes the nine address bits required to designate a byte
address within the page.
For the “Power of 2” binary page size (256-bytes), the Buffer addressing is referenced in the
datasheet using the conventional terminology BFA7 - BFA0 to denote the 8 address bits
required to designate a byte address within a buffer. Main memory addressing is referenced
using the terminology A16 - A0, where A16 - A8 denotes the nine address bits required to desig-
nate a page address and A7 - A0 denotes the eight address bits required to designate a byte
address within a page.
4 AT45DB011D
3639K–DFLASH–6/2014

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AT45DB011D-SH-SL955 전자부품, 판매, 대치품
AT45DB011D
operation. Following the don’t care bytes, additional pulses on SCK result in data being output
on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the
address bytes, the don’t care bytes, and the reading of data. When the end of a page in main
memory is reached, the device will continue reading back at the beginning of the same page. A
low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin
(SO). The maximum SCK frequency allowable for the Main Memory Page Read is defined by the
fSCK specification. The Main Memory Page Read bypasses the data buffer and leaves the con-
tents of the buffer unchanged.
6.5 Buffer Read
The SRAM data buffer can be accessed independently from the main memory array, and utiliz-
ing the Buffer Read Command allows data to be sequentially read directly from the buffer. Two
opcodes, D4H or D1H, can be used for the Buffer Read Command. The use of each opcode
depends on the maximum SCK frequency that will be used to read data from the buffer. The
D4H opcode can be used at any SCK frequency up to the maximum specified by fCAR1. The D1H
opcode can be used for lower frequency read operations up to the maximum specified by fCAR2.
To perform a buffer read from the DataFlash standard buffer (264-bytes), the opcode must be
clocked into the device followed by three address bytes comprised of 15 don’t care bits and
nine buffer address bits (BFA8 - BFA0). To perform a buffer read from the binary buffer (256-
bytes), the opcode must be clocked into the device followed by three address bytes comprised
of 16 don’t care bits and eight buffer address bits (BFA7 - BFA0). Following the address bytes,
one don’t care byte must be clocked in to initialize the read operation. The CS pin must remain
low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of
data. When the end of a buffer is reached, the device will continue reading back at the beginning
of the buffer. A low-to-high transition on the CS pin will terminate the read operation and tri-state
the output pin (SO).
7. Program and Erase Commands
7.1 Buffer Write
Data can be clocked in from the input pin (SI) into the buffer. To load data into the DataFlash
standard buffer (264-bytes), a 1-byte opcode, 84H, must be clocked into the device followed by
three address bytes comprised of 15 don’t care bits and 9 buffer address bits (BFA8 - BFA0).
The nine buffer address bits specify the first byte in the buffer to be written. To load data into the
binary buffers (256-bytes each), a 1-byte opcode, 84H, must be clocked into the device followed
by three address bytes comprised of 16 don’t care bits and eight buffer address bits (BFA7 -
BFA0). The eight buffer address bits specify the first byte in the buffer to be written. After the last
address byte has been clocked into the device, data can then be clocked in on subsequent clock
cycles. If the end of the data buffer is reached, the device will wrap around back to the beginning
of the buffer. Data will continue to be loaded into the buffer until a low-to-high transition is
detected on the CS pin.
7.2 Buffer to Main Memory Page Program with Built-in Erase
Data written into the buffer can be programmed into the main memory. A 1-byte opcode, 83H,
must be clocked into the device. For the DataFlash standard page size (264-bytes), the opcode
must be followed by three address bytes consist of five don’t care bits, nine page address bits
(PA8 - PA0) that specify the page in the main memory to be written and nine don’t care bits. To
perform a buffer to main memory page program with built-in erase for the binary page size (256-
3639K–DFLASH–6/2014
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