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AT45DB161E-MHF-T 데이터시트 PDF




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기능 2.3V or 2.5V Minimum SPI Serial Flash Memory
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AT45DB161E-MHF-T 데이터시트, 핀배열, 회로
Atmel AT45DB161E
16-Mbits DataFlash (with Extra 512-Kbits), 2.3V or 2.5V Minimum
SPI Serial Flash Memory
Features
PRELIMINARY DATASHEET
Single 2.3V - 3.6V or 2.5V - 3.6V supply
Serial Peripheral Interface (SPI) compatible
Supports SPI modes 0 and 3
Supports Atmel® RapidSoperation
Continuous Read capability through entire array
Up to 85MHz
Low-power Read option up to 10MHz
Clock-to-output time (tV) of 6ns maximum
User configurable page size
512 bytes per page
528 bytes per page (default)
Page size can be factory pre-configured for 512 bytes
Two fully independent SRAM data buffers (512/528 bytes)
Allows receiving data while reprogramming the Main Memory Array
Flexible programming options
Byte/Page program (1 to 512/528 bytes) directly into main memory
Buffer Write
Buffer to Main Memory Page Program
Flexible Erase options
Page Erase (512/528 bytes)
Block Erase (4KB)
Sector Erase (128KB)
Chip Erase (16-Mbits)
Program and Erase Suspend/Resume
Advanced hardware and software data protection features
Individual sector protection
Individual sector lockdown to make any sector permanently read-only
128-byte, One-Time Programmable (OTP) Security Register
64 bytes factory programmed with a unique identifier
64 bytes user programmable
Software controlled reset
JEDEC Standard Manufacturer and Device ID Read
Low-power dissipation
500nA Ultra-Deep Power-Down current (typical)
3μA Deep Power-Down current (typical)
25μA Standby current (typical)
11mA Active Read current (typical)
Endurance: 100,000 program/erase cycles per page minimum
Data retention: 20 years
Complies with full industrial temperature range
Green (Pb/Halide-free/RoHS compliant) packaging options
8-lead SOIC (0.150" wide)
8-pad Ultra-thin DFN (5 x 6 x 0.6mm)
9-ball Chip-scale BGA (5 x 5 x 1.2mm)
8782A–DFLASH–3/12




AT45DB161E-MHF-T pdf, 반도체, 판매, 대치품
2. Block Diagram
Figure 2-1. Block Diagram
WP
Page (512/528 bytes)
Flash Memory Array
SCK
CS
RESET
VCC
GND
Buffer 1 (512/528 bytes)
Buffer 2 (512/528 bytes)
I/O Interface
SI SO
Atmel AT45DB161E [PRELIMINARY DATASHEET]
8782A–DFLASH–3/12
4

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AT45DB161E-MHF-T 전자부품, 판매, 대치품
5. Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from either one of the two SRAM data
buffers. The DataFlash supports RapidS protocols for Mode 0 and Mode 3. Please see Section 25. Detailed Bit-level
Read Waveforms: Atmel RapidS Mode 0/Mode 3 diagrams in this datasheet for details on the clock cycle sequences for
each mode.
5.1 Continuous Array Read (Legacy Command: E8h Opcode)
By supplying an initial starting address for the Main Memory Array, the Continuous Array Read command can be utilized
to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional
addressing information or control signals need to be provided. The DataFlash incorporates an internal address counter
that will automatically increment on every clock cycle, allowing one Continuous Read operation without the need of
additional address sequenced. To perform a Continuous Read from the standard DataFlash page size (528 bytes), an
opcode of E8h must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte
address sequence) and four dummy bytes. The first 12 bits (PA11 - PA0) of the 22-bit address sequence specify which
page of the Main Memory Array to read and the last 10 bits (BA9 - BA0) of the 22-bit address sequence specify the
starting byte address within the page. To perform a Continuous Read from the binary page size (512 bytes), an opcode of
E8h must be clocked into the device followed by three address bytes and four dummy bytes. The first
12 bits (A20 - A9) of the 21-bit sequence specify which page of the Main Memory Array to read and the last nine bits
(A8 - A0) of the 21-bit address sequence specify the starting byte address within the page. The dummy bytes that follow
the address bytes are needed to initialize the read operation. Following the dummy bytes, additional clock pulses on the
SCK pin will result in data being output on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of
data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue
reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from
the end of one page to the beginning of the next page). When the last bit in the Main Memory Array has been read, the
device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no
delays will be incurred when wrapping around from the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum
SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array Read
bypasses the data buffers and leaves the contents of the buffers unchanged.
Note:
This command is not recommended for new designs.
5.2 Continuous Array Read (High Frequency Mode: 1Bh Opcode)
This command can be used with the serial interface to read the Main Memory Array sequentially in very High-Speed (HS)
mode for any clock frequency up to the maximum specified by fCAR1. To perform a Continuous Read Array with the
standard DataFlash page size (528 bytes), the CS must first be asserted then an opcode 1Bh must be clocked into the
device followed by three address bytes and two dummy bytes. The first 12 bits (PA11 - PA0) of the 22-bit address
sequence specify which page of the Main Memory Array to read and the last 10 bits (BA9 - BA0) of the 22-bit address
sequence specify the starting byte address within the page. To perform a Continuous Read with the binary page size
(512 bytes), the opcode 1Bh must be clocked into the device followed by three address bytes (A20 - A0) and two dummy
bytes. Following the dummy bytes, additional clock pulses on the SCK pin will result in data being output on the SO
(Serial Output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, the dummy bytes, and the reading of
data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue
reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover
from the end of one page to the beginning of the next page). When the last bit in the Main Memory Array has been read,
the device will continue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.
Atmel AT45DB161E [PRELIMINARY DATASHEET]
8782A–DFLASH–3/12
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부품번호상세설명 및 기능제조사
AT45DB161E-MHF-T

2.3V or 2.5V Minimum SPI Serial Flash Memory

ATMEL Corporation
ATMEL Corporation
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2.3V or 2.5V Minimum SPI Serial Flash Memory

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