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부품번호 | ADP3207D 기능 |
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기능 | 7-Bit Programmable Multi-Phase Mobile CPU Synchronous Buck Controller | ||
제조업체 | ON Semiconductor | ||
로고 | |||
전체 30 페이지수
ADP3207D
7-Bit Programmable,
Multi-Phase Mobile, CPU
Synchronous Buck
Controller
The ADP3207D is a high efficiency, multi−phase, synchronous,
buck−switching regulator controller optimized for converting
notebook battery voltage into the core supply voltage required by high
performance Intel processors. The part uses an internal 7−bit
Digital−to−Analog Converter (DAC) to read Voltage Identification
(VID) code directly from the processor that sets the output voltage.
The phase relationship of the output signals can be programmed to
provide 1−, 2−, or 3−phase operation, allowing for the construction of
up to three interleaved buck−switching stages.
The ADP3207D uses a multi−mode architecture to drive the
logic−level PWM outputs at a programmable switching frequency that
can be optimized depending on the output current requirement. The
part switches between multi−phase and single−phase operation to
maximize its effectiveness under all load conditions. In addition, the
ADP3207D includes a programmable slope function to adjust the
output voltage as a function of the load current. As a result, it is always
best positioned for a system transient.
The chip also provides accurate and reliable short−circuit
protection, adjustable current limiting, and a delayed power−good
output that accommodates On−the−Fly (OTF) output voltage changes
requested by the CPU.
The ADP3207D is specified over the extended commercial
temperature range of −10°C to 100°C and is available in a 40−lead
LFCSP.
The ADP3207DF has a soft−start time one tenth of ADP3207D.
There are no other differences between the ADP3207D and
ADP3207DF.
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LFCSP40
CASE 932AC
MARKING DIAGRAM
ADP3207D
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YYWW = Date Code
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 31 of this data sheet.
Features
• 1−, 2−, or 3−Phase Operation at Up to 750 kHz per Phase
• $7 mV Worst−Case Differential Sensing Error
Overtemperature
• Input Voltage Range of 3.3 V to 22 V
• Interleaved PWM Outputs for Driving External High
Power MOSFET Drivers
• Enhanced PWM FlexModet for Excellent Load
Transient Performance
• Automatic Power−Saving Modes Maximize Efficiency
During Light Load and Deeper Sleep Operation
• Soft Transient Control Reduces Inrush Current and
Audio Noise
• Active Current Balancing Between Output Phases
• Independent Current Limit and Load Line Setting
Inputs for Additional Design Flexibility
• Built−In, Power−Good Masking Supports VID OTF
• 7−Bit Digitally Programmable 0.3 V to 1.5 V Output
• Overload and Short−Circuit Protection Latchoff Delay
• Built−In, Clock Enable Output Delays CPU Clock Until
CPU Supply Voltage Stabilizes
• Current Monitor Output Signals the Total Output Power
of the Buck Converter
• This is a Pb−Free Device
Applications
• Notebook Power Supplies for Next Generation
Intel® Processors
© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 0
1
Publication Order Number:
ADP3207D/D
ADP3207D
PIN FUNCTION DESCRIPTIONS
Pin No
1
Mnemonic
EN
Description
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD
output low.
2
PWRGD
Power−Good Output. Open−drain output that signals when the output voltage is outside of the proper
operating range. The pull−high voltage on this pin cannot be higher than VCC.
3
IMON
Current Monitor Output. This pin sources a current proportional to the output load current. A resistor to
FBRTN sets the current monitor gain.
4
CLKEN
Clock Enable Output. The pull−high voltage on this pin cannot be higher than VCC.
5
FBRTN
Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
6 FB Feedback Input. Error amplifier input for remote sensing of the output voltage.
7
COMP
Error Amplifier Output and Compensation Point.
8 NC Not Connected.
9
RPM
RPM Mode Timing Control Input. A resistor between this pin to ground sets the RPM mode turn−on
threshold voltage.
10
DPRSLP
Deeper Sleep Control Input.
11
IREF
This pin sets the internal bias currents. A 80kW resistor is connected from this pin to ground.
12
ILIMP
Current Limit Set. An external resistor from ILIMN to ILIMP sets the current limit threshold of the converter.
13
ILIMN
Current Limit Set. An external resistor from ILIMN to ILIMP sets the current limit threshold of the converter.
14 RT Multi−phase Frequency Setting Input. An external resistor connected between this pin and GND sets the
oscillator frequency of the device when operating in multi−phase PWM mode.
15 RAMPADJ PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal
PWM ramp.
16
LLSET
Output Load Line Programming Input. The center point of a resistor divider between CSREF and
CSCOMP is connected to this pin to set the load line slope.
17
CSREF
Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current
sense amplifier and the power−good and crowbar functions. This pin should be connected to the common
point of the output inductors.
18
CSSUM
Current Sense Summing Node. External resistors from each switch node to this pin sum the inductor
currents together to measure the total output current.
19
CSCOMP
Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the gain of
the current sense amplifier and the positioning loop response time.
20
21 to
23
GND
SW3 to SW1
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused
phases should be left open.
24 to
26
PWM3 to
PWM1
Logic−Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as
the ADP3611. Connecting the PWM2 and/or PWM3 outputs to VCC causes that phase to turn off, allowing
the ADP3207D to operate as a 1−, 2−, or 3−phase controller.
27 OD Multi−phase Output Disable Logic Output. This pin is actively pulled low when the ADP3207D enters
single−phase mode or during shutdown. Connect this pin to the SD inputs of the Phase 2 and Phase 3
MOSFET drivers.
28
DCM
Discontinuous Current Mode Enable Output. This pin is actively pulled low when the single−phase inductor
current crosses zero.
29
VRTT
Voltage Regulator Thermal Throttling Logic Output. This pin goes high if the temperature at the monitoring
point connected to TTSENSE exceeds the programmed VRTT temperature threshold.
30 TTSENSE Thermal Throttling Sense Input and OVP Disable. The center point of a resistor divider (where the lower
resistor is an NTC thermistor) between VCC and GND is connected to this pin to remotely sense the
temperature at the desired thermal monitoring point. Connect TTSENSE VCC if Thermal Throttling is not used.
31
VCC
Supply Voltage for the Device.
32 PSI Power State Indicator Input. Pulling this pin to GND forces the ADP3207D to operate in single−phase
mode.
33
34 to
40
DRPSTP
VID6 to VID0
Deeper Stop Control Input.
Voltage Identification DAC Inputs. When in normal operation mode, the DAC output programs the FB
regulation voltage from 0.3 V to 1.5 V (see Table 3).
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4
4페이지 ADP3207D
ELECTRICAL CHARACTERISTICS VCC = 5.0 V, FBRTN = GND, EN = VCC, VVID = 0.50 V to 1.5000 V, PSI = 1.05 V,
DPRSLP = GND, DPRSTP= 1.05 V, LLSET = CSREF, TA = −10°C to 100°C, unless otherwise noted (Note 1). RREF = 80 kW.
Current entering a pin (sunk by the device) has a positive sign.
Parameter
Symbol
Conditions
Min Typ
CURRENT MONITOR
Current Gain Accuracy
IMON/ILIM
Measured from ILIMP to IMON
ILIM = −20 mA
ILIM = −10 mA
IMON Clamp Voltage
VMAXMON
Relative to FBRTN, ILIMP = −30 mA
PULSE WIDTH MODULATOR − Clock Oscillator
9.3 10
9.2 10
1.05
RT Voltage
PWM Clock Frequency
Range (Note 2)
VRT RT = 125 kW, VVID = 1.4000 V
See also VRT(VVID) formula
fCLK Operating Range
1.12 1.2
0.3
PWM Clock Frequency
RAMP GENERATOR
fCLK TA = +25°C, VVID = 1.2000 V
RT = 73 kW
RT = 125 kW
RT = 180 kW
1150
500
1450
850
630
RAMP Voltage
RAMP Current Range
(Note 2)
VRAMP
IRAMP
EN = high, IRAMP = 30 mA
EN = low
EN = high
EN = low, RAMP = 19 V
0.9
1.0
−0.5
1.0
VIN
PWM COMPARATOR
PWM Comparator Offset
(Note 2)
VOSRPM
VRAMP − VCOMP
−3.0
RPM COMPARATOR
RPM Current
RPM Comparator Offset
(Note 2)
IRPM
VOSRPM
VVID = 1.2 V, RT = 125 kW
See also IRPM(RT) formula
VCOMP − (1 +VRPM)
−3.0
−8.8
EPWM CLOCK SYNC
Trigger Threshold (Note 2)
Relative to COMP sampled TCLK earlier
3−phase configuration
2−phase configuration
1−phase configuration
300
350
400
SWITCH AMPLIFIER
SW Common Mode Range
(Note 2)
VSW(X)CM
Operating Range for current sensing
−600
SW Input Resistance
RSW(X)
SWX = 0 V
ZERO CURRENT SWITCHING COMPARATOR
20 32
SW ZCS Threshold
Masked Off Time
VDCM(SW1)
tOFFMSKD
DCM mode, DPRSLP = 3.3 V
Measured from PWM neg edge to PWM Pos
Edge at max frequency of operation
−4.0
700
SYSTEM I/O BUFFERS VID[6:0], PSI INPUTS
Input Voltage
Input Current
VID Delay Time (Note 2)
Refers to driving signal level
Logic low, Isink w 1 mA
Logic high, Isource v −5 mA
V = 0.2 V
VID[6:0], DPRSLP (active pulldown to GND)
PSI (active pullup to VCC)
Any VID edge to FB change 10%
0.7
−1.0
+2.0
200
1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2. Guaranteed by design or bench characterization, not production tested.
Max
10.7
10.8
1.15
1.28
3.0
1750
780
1.1
100
+0.5
3.0
3.0
+200
45
0.3
Unit
V
V
MHz
kHz
V
mA
mV
mA
mV
mV
mV
kW
mV
ns
V
mA
ns
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부품번호 | 상세설명 및 기능 | 제조사 |
ADP3207 | 7-Bit Programmable Multiphase Mobile CPU Synchronous Buck Controller | ANALOG DEVICES |
ADP3207 | 7-Bit Programmable Multiphase Mobile CPU Synchronous Buck Controller | ON Semiconductor |
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