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A3PN125 데이터시트 PDF




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부품번호 A3PN125 기능
기능 ProASIC3 nano Flash FPGAs
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A3PN125 데이터시트, 핀배열, 회로
Revision 11
ProASIC3 nano Flash FPGAs
Features and Benefits
Wide Range of Features
• 10 k to 250 k System Gates
• Up to 36 kbits of True Dual-Port SRAM
• Up to 71 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Instant On Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
In-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock® Designed to Secure FPGA Contents
Low Power
• Low Power ProASIC®3 nano Products
• 1.5 V Core Voltage for Low Power
• Support for 1.5 V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Advanced I/Os
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• I/O Registers on Input, Output, and Enable Paths
• Selectable Schmitt Trigger Inputs
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rateand Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL
• Up to Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay
Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• True Dual-Port SRAM (except ×18 organization)
Enhanced Commercial Temperature Range
• –20°C to +70°C
Table 1 • ProASIC3 nano Devices
ProASIC3 nano Devices
A3PN010 A3PN0151 A3PN020
A3PN060 A3PN125
ProASIC3 nano-Z Devices1
A3PN030Z1,2 A3PN060Z1 A3PN125Z1
System Gates
10,000
15,000 20,000
30,000
60,000
125,000
Typical Equivalent Macrocells
86 128 172
256
512 1,024
VersaTiles (D-flip-flops)
RAM Kbits (1,024 bits)2
4,608-Bit Blocks2
260 384 520
768
1,536
3,072
– – – – 18 36
– ––
48
FlashROM Kbits
Secure (AES) ISP2
Integrated PLL in CCCs2
1 11
1
11
– – – – Yes Yes
– ––
11
VersaNet Globals
4 4 4 6 18 18
I/O Banks
2 33
2
22
Maximum User I/Os (packaged device)
34
49
49
77
71 71
Maximum User I/Os (Known Good Die)
34
– 52
83
71 71
Package Pins
QFN
VQFP
QN48
QN68
QN68 QN48, QN68
VQ100
VQ100
VQ100
Notes:
1. Not recommended for new designs.
2. A3PN030Z and smaller devices do not support this feature.
3. For higher densities and support of additional features, refer to the ProASIC3 and ProASIC3E datasheets.
A3PN250
A3N250Z1
250,000
2,048
6,144
36
8
1
Yes
1
18
4
68
68
VQ100
† A3PN030 and smaller devices do not support this feature.
January 2013
© 2013 Microsemi Corporation
I




A3PN125 pdf, 반도체, 판매, 대치품
The actual mark will vary by the device/package combination ordered.
Device Name
(six characters)
Package
Wafer Lot #
ACTELXXX
AGL030YWW
UCG81XXXX
XXXXXXXX
Country of Origin
Date Code
Customer Mark
(if applicable)
Figure 1 • Example of Device Marking for Small Form Factor Packages
ProASIC3 nano Products Available in the Z Feature Grade
Devices
A3PN030*
Packages
QN48
QN68
VQ100
Note: *Not recommended for new designs.
A3PN060*
VQ100
A3PN125*
VQ100
A3PN250*
VQ100
Temperature Grade Offerings
ProASIC3 nano Devices
A3PN010 A3PN015* A3PN020
ProASIC3 nano-Z Devices*
QN48
C, I – –
QN68
– C, I C, I
VQ100
– ––
Note: *Not recommended for new designs.
C = Commercial temperature range: 0°C to 70°C ambient temperature
I = Industrial temperature range: –40°C to 85°C ambient temperature
A3PN030Z*
C, I
C, I
C, I
A3PN060 A3PN125 A3PN250
A3PN060Z* A3PN125Z* A3PN250Z*
–––
–––
C, I C, I C, I
Speed Grade and Temperature Grade Matrix
Temperature Grade
C1
I2
Notes:
1. C = Commercial temperature range: 0°C to 70°C ambient temperature.
2. I = Industrial temperature range: –40°C to 85°C ambient temperature.
Contact your local Microsemi SoC Products Group representative for device availability:
http://www.microsemi.com/soc/contact/default.aspx.
Std.
IV Revision 11

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A3PN125 전자부품, 판매, 대치품
1 – ProASIC3 nano Device Overview
General Description
ProASIC3, the third-generation family of Microsemi flash FPGAs, offers performance, density, and
features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3 nano
devices the advantage of being a secure, low power, single-chip solution that is Instant On. ProASIC3
nano devices are reprogrammable and offer time-to-market benefits at an ASIC-level unit cost. These
features enable designers to create high-density systems using existing ASIC or FPGA design flows and
tools.
ProASIC3 nano devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well
as clock conditioning circuitry based on an integrated phase-locked loop (PLL). A3PN030 and smaller
devices do not have PLL or RAM support. ProASIC3 nano devices have up to 250,000 system gates,
supported with up to 36 kbits of true dual-port SRAM and up to 71 user I/Os.
ProASIC3 nano devices increase the breadth of the ProASIC3 product line by adding new features and
packages for greater customer value in high volume consumer, portable, and battery-backed markets.
Added features include smaller footprint packages designed with two-layer PCBs in mind, low power,
hot-swap capability, and Schmitt trigger for greater flexibility in low-cost and power-sensitive applications.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-
based FPGAs, flash-based ProASIC3 nano devices allow all functionality to be Instant On; no external
boot PROM is required. On-board security mechanisms prevent access to all the programming
information and enable secure remote updates of the FPGA logic. Designers can perform secure remote
in-system reprogramming to support future design iterations and field upgrades with confidence that
valuable intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using
the industry-standard AES algorithm. The ProASIC3 nano device architecture mitigates the need for
ASIC migration at higher user volumes. This makes the ProASIC3 nano device a cost-effective ASIC
replacement solution, especially for applications in the consumer, networking/communications,
computing, and avionics markets.
With a variety of devices under $1, ProASIC3 nano FPGAs enable cost-effective implementation of
programmable logic and quick time to market.
Security
Nonvolatile, flash-based ProASIC3 nano devices do not require a boot PROM, so there is no vulnerable
external bitstream that can be easily copied. ProASIC3 nano devices incorporate FlashLock, which
provides a unique combination of reprogrammability and design security without external overhead,
advantages that only an FPGA with nonvolatile flash programming can offer.
ProASIC3 nano devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest
level of protection in the FPGA industry for programmed intellectual property and configuration data. In
addition, all FlashROM data in ProASIC3 nano devices can be encrypted prior to loading, using the
industry-leading AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was
adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977
DES standard. ProASIC3 nano devices have a built-in AES decryption engine and a flash-based AES
key that make them the most comprehensive programmable logic device security solution available
today. ProASIC3 nano devices with AES-based security provide a high level of protection for remote field
updates over public networks such as the Internet, and are designed to ensure that valuable IP remains
out of the hands of system overbuilders, system cloners, and IP thieves.
Revision 11
1-1

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