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HCPL-3700SD 데이터시트 PDF




Fairchild Semiconductor에서 제조한 전자 부품 HCPL-3700SD은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 HCPL-3700SD 기능
기능 AC/DC TO LOGIC INTERFACE OPTOCOUPLER
제조업체 Fairchild Semiconductor
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HCPL-3700SD 데이터시트, 핀배열, 회로
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
DESCRIPTION
The HCPL-3700 voltage/current threshold detection optocoupler consists of an
AlGaAs LED connected to a threshold sensing input buffer IC which are optically
coupled to a high gain darlington output. The input buffer chip is capable of con-
trolling threshold levels over a wide range of input voltages with a single resistor.
The output is TTL and CMOS compatible.
FEATURES
• AC or DC input
• Programmable sense voltage
• Logic level compatibility
• Threshold guaranteed over temperature
TRUTH TABLE
(Positive Logic)
(0°C to 70°C)
• Optoplanar™ construction for high
Input
Output
common mode immunity
• UL recognized (file # E90700)
APPLICATIONS
• Low voltage detection
• 5 V to 240 V AC/DC voltage sensing
• Relay contact monitor
HL
LH
A 0.1 µF bypass capacitor
must be connected between
pins 8 and 5.
• Current sensing
• Microprocessor Interface
• Industrial controls
AC/DC
POWER
RX
HCPL-3700
LOGIC
GND 1
GND 2
8
8
1
AC 1
DC+ 2
DC- 3
AC 4
1
8
ABSOLUTE MAXIMUM RATINGS (No derating required up to 70°C)
Parameter
Storage Temperature
Operating Temperature
Lead Solder Temperature
EMITTER
Average
Input Current Surge
Transient
Input Voltage (Pins 2-3)
Input Power Dissipation
Total Package Power Dissipation
DETECTOR
Output Current (Average)
Supply Voltage (Pins 8-5)
Output Voltage (Pins 6-5)
Output Power Dissipation
3 ms, 120 Hz Pulse Rate
10 µs, 120 Hz Pulse Rate
(Note 1)
(Note 2)
(Note 3)
(Note 4)
Symbol
TSTG
TOPR
TSOL
IIN
VIN
PIN
PT
IO
VCC
VO
PO
Value
-55 to +125
-40 to +85
260 for 10 sec
50 (MAX)
140 (MAX)
500 (MAX)
-0.5 (MIN)
230 (MAX)
305 (MAX)
30 (MAX)
-0.5 to 20
-0.5 to 20
210 (MAX)
1
8 VCC
7 NC
6 VO
5 GND
Units
°C
°C
°C
mA
V
mW
mW
mA
V
V
mW
© 2003 Fairchild Semiconductor Corporation
Page 1 of 11
11/8/04




HCPL-3700SD pdf, 반도체, 판매, 대치품
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
NOTES
1. Derate linearly above 70°C free-air temperature at a rate of 1.8 mW/°C.
2. Derate linearly above 70°C free-air temperature at a rate of 2.5 mW/°C.
3. Derate linearly above 70°C free-air temperature at a rate of 0.6 mA/°C.
4. Derate linearly above 70°C free-air temperature at a rate of 1.9 mW/°C.
5. Logic low output level at pin 6 occurs when VINVTH+ and when VIN>VTH- once VIN exceeds VTH+. Logic high output level at pin
6 occurs when VINVTH- and when VIN<VTH+ once VIN decreases below VTH-.
6. TPHL propagation delay is measured from the 2.5 V level of the leading edge of a 5.0 V input pulse (1 µs rise time) to the 1.5 V
level on the leading edge of the output pulse. TPLH propagation delay is measured on the trailing edges of the input and output
pulse. (Refer to Fig. 9)
7. Common mode transient immunity in logic high level is the maximum tolerable (positive) dVcm/dt on the leading edge of the
common mode pulse signal VCM, to assure that the output will remain in a logic high state (i.e., VO>2.0 V). Common mode
transient immunity in logic low level is the maximum tolerable (negative) dVcm/dt on the trailing edge of the common mode
pulse signal, VCM, to assure that the output will remain in a logic low state (i.e., VO<0.8 V). (Refer to Fig.10)
8. In applications where dVcm/dt may exceed 50,000 V/µs (Such as static discharge), a series resistor, RCC, should be included to
protect the detector chip from destructive surge currents. The recommended value for RCC is 240 V per volt of allowable drop
in VCC (between pin 8 and VCC) with a minimum value of 240 .
9. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted together.
10. The 2500 VRMS/1 min. capability is validated by a 3.0 kVRMS/1 sec. dielectric voltage withstand test.
11. AC voltage is instantaneous voltage for VTH+ & VTH-.
12. All typicals at TA = 25°C, VCC = 5 V unless otherwise specied.
© 2003 Fairchild Semiconductor Corporation
Page 4 of 11
11/8/04

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HCPL-3700SD 전자부품, 판매, 대치품
AC/DC TO LOGIC INTERFACE
OPTOCOUPLER
HCPL-3700
+5V
Pulse
Generator
tr = 5ns
ZO= 50
1 AC
2 DC+
3 DC-
VCC 8
7
VO 6
.1uf
bypass
4 AC GND 5
RL
Output
(VO )
Input
(VIN)
t PHL
Output
(VO )
90%
10%
VIN
Pulse Amplitude = 50 V
Pulse Width = 1 ms
f = 100 Hz
Tr = Tf = 1.0 µs (10 - 90%)
tr
Fig. 9. Switching Test Circuit
5V
2.5V
t PLH
0V
VO
90%
10%
1.5 V
VOL
tf
VFF
I IN
A
B
1 AC
VCC 8
2 DC+
7
3 DC-
VO 6
4 AC GND 5
+ V-CM
Pulse Gen
.1uf
bypass
RCC*
+5V
RL
Output
(VO )
CL**
VCM
VO
* SEE NOTE 8
Switching Pos. (A)
IIN = 0 mA
VO (Min)
VCM H
VCM L
5V
5V CMH
** CL IS 30 pF, WHICH INCLUDES PROBE
AND STRAY WIRING CAPACITANCE
VO
VO (Max)
Switching Pos. (B)
IIN = 3.11 mA
VOL CML
Fig. 10. Test Circuit for Common Mode Transient Immunity and Typical Waveforms
© 2003 Fairchild Semiconductor Corporation
Page 7 of 11
11/8/04

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관련 데이터시트

부품번호상세설명 및 기능제조사
HCPL-3700S

AC/DC TO LOGIC INTERFACE OPTOCOUPLER

Fairchild Semiconductor
Fairchild Semiconductor
HCPL-3700SD

AC/DC TO LOGIC INTERFACE OPTOCOUPLER

Fairchild Semiconductor
Fairchild Semiconductor

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