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PDF HCPL0738 Data sheet ( Hoja de datos )
| Número de pieza | HCPL0738 | |
| Descripción | High Speed CMOS Optocoupler | |
| Fabricantes | Agilent(Hewlett-Packard) | |
| Logotipo | .gif "Agilent(Hewlett-Packard)"){kind=logo} |
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Agilent HCPL-0738
High Speed CMOS Optocoupler
Data Sheet
Description
The HCPL-0738 is a dual-channel
15 MBd CMOS optocoupler in
SOIC-8 package. The HCPL-0738
optocoupler utilizes the latest CMOS
IC technology to achieve out-
standing performance with very low
power consumption. Basic building
blocks of HCPL-0738 are high
speed LEDs and CMOS detector ICs.
Agilent also offers the same
performance in the single channel
version, HCPL-0708. Each
detector incorporates an
integrated photodiode, a high
speed transimpedance amplifier,
and a voltage comparator with an
output driver.
Functional Diagram
ANODE 1 1
CATHODE 1 2
CATHODE 2 3
ANODE 2 4
8 VDD
7 VO 1
6 VO 2
5 GND
Truth Table
LED VO, Output
OFF H
ON L
Note: A 0.1 µF bypass capacitor must be
connected between pins 5 and 8.
Features
• 15 ns typical pulse width
distortion
• 40 ns maximum prop. delay skew
• 20 ns typical prop. delay
• High speed: 15 MBd
• + 5 V CMOS compatibility
• 10 kV/µS minimum common mode
rejection
• –40 to 100˚C temperature range
• Safety and regulatory approvals
–UL recognized (2500 V rms for
1 minute per UL 1577)
–CSA component acceptance
notice #5.
–VDE 0884 (TUV) approved for
HCPL-0738 Option 060
Applications
• PDP (plasma display panel)
• Digital field bus isolation:
DeviceNet, SDS, Profibus
• Multiplexed data transmission
• Computer peripheral interface
• Microprocessor system interface
• DC/DC converter
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD.
1 page  
Package Characteristics
All typicals at TA = 25˚C.
Parameter
Symbol
Min.
Typ.
Max.
Units Test Conditions
Input-Output Insulation
I I-O
Input-Output Momentary
Withstand Voltage
Input-Output Resistance
Input-Output Capacitance
VISO
RI-O
CI-O
1
2500
1012
0.6
µA
V rms
Ω
pF
45% RH, t = 5 s
VI-O = 3 kV DC,
TA = 25˚C
RH ≤ 50%, t = 1 min.,
TA = 25˚C
VI-O = 500 V DC
f = 1 MHz, TA = 25˚C
Notes:
1. tPHL propagation delay is measured from the 50% level on the rising edge of the input pulse to the 2.5 V level of the falling edge of the VO signal.
tPLH propagation delay is measured from the 50% level on the falling edge of the input pulse to the 2.5 V level of the rising edge of the VO signal.
2. PWD is defined as |tPHL - tPLH|.
3. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the
recommended operating conditions.
4. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.
5. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
1000
100
10
1.0
IF
+
VF
–
TA = 25°C
0.1
0.01
0.001
1.1 1.2 1.3 1.4 1.5 1.6
VF – FORWARD VOLTAGE – V
8
7 VDD = 5.0 V
IOL = 20 µA
6
5
4 Ith1
Ith2
3
2
1
0
-40 -20 0 20 40 60 80 100
TA – TEMPERATURE – °C
10.0
VDD = 5.0 V
9.5
9.0
8.5
Iddh
8.0
7.5
7.0
6.5
6.0
-40 -20 0 20 40 60 80 100
TA – TEMPERATURE – °C
Figure 1. Typical input diode forward
characteristic.
Figure 2. Typical input threshold current vs.
temperature.
Figure 3. Typical logic high O/P supply
current vs. temperature.
11.6
11.4
VDD = 5.0 V
11.2
11.0
10.8
10.6
10.4
Iddl
10.2
10.0
9.8
9.6
-40 -20 0 20 40 60 80 100
TA – TEMPERATURE – °C
50
45
40
Tphl CH 1
35
Tphl CH 2
30
25
20
15 PWD CH 1
Tplh CH 1
Tplh CH 2
PWD CH 2
10
5 VDD = 5.0 V
TA = 25 °C
0
567 8
9 10 11 12 13 14
IF – PULSE INPUT CURRENT – mA
Figure 4. Typical logic low O/P supply
current vs. temperature.
Figure 5. Typical switching speed vs. pulse
input current.
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet HCPL0738.PDF ] | |
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