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PDF BUK96E04-40A Data sheet ( Hoja de datos )
| Número de pieza | BUK96E04-40A | |
| Descripción | TrenchMOS logic level FET | |
| Fabricantes | NXP Semiconductors | |
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BUK95/96/9E04-40A
TrenchMOS™ logic level FET
Rev. 01 — 24 October 2001
Product data
1. Description
N-channel enhancement mode field-effect power transistor in a plastic package using
TrenchMOS™ technology, featuring very low on-state resistance.
Product availability:
BUK9504-40A in SOT78 (TO-220AB); BUK9604-40A in SOT404 (D 2-PAK);
BUK9E04-40A in SOT226 (I2-PAK).
2. Features
s TrenchMOS™ technology
s Q101 compliant
s 175 °C rated
s Logic level compatible.
3. Applications
s Automotive and general purpose power switching:
x 12 V loads
x Motors, lamps and solenoids.
4. Pinning information
Table 1: Pinning - SOT78, SOT404, SOT226 simplified outline and symbol
Pin Description
Simplified outline
1 gate (g)
2 drain (d) [1] mb
mb
mb
3 source (s)
mb mounting base,
connected to
drain (d)
MBK106
123
SOT78 (TO-220AB)
2
1 3 MBK116
123
MBK112
SOT404 (D2-PAK) SOT226 (I2-PAK)
Symbol
g
MBB076
d
s
[1] It is not possible to make connection to pin 2 of the SOT404 package.
1 page  
Philips Semiconductors
BUK95/96/9E04-40A
TrenchMOS™ logic level FET
8. Characteristics
Table 5: Characteristics
Tj = 25 °C unless otherwise specified
Symbol Parameter
Conditions
Static characteristics
V(BR)DSS
VGS(th)
drain-source breakdown
voltage
ID = 0.25 mA; VGS = 0 V
Tj = 25 °C
Tj = −55 °C
gate-source threshold voltage ID = 1 mA; VDS = VGS;
Figure 9
IDSS
IGSS
RDSon
drain-source leakage current
gate-source leakage current
drain-source on-state
resistance
Tj = 25 °C
Tj = 175 °C
Tj = −55 °C
VDS = 40 V; VGS = 0 V
Tj = 25 °C
Tj = 175 °C
VGS = ±10 V; VDS = 0 V
VGS = 5 V; ID = 25 A;
Figure 7 and 8
Dynamic characteristics
Tj = 25 °C
Tj = 175 °C
VGS = 4.3 V; ID = 25 A
VGS = 10 V; ID = 25 A
Qg(tot)
Qgs
Qgd
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
Ld
total gate charge
gate-to-source charge
gate-to-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
internal drain inductance
VGS = 5 V; VDD = 32 V;
ID = 25 A; Figure 14
VGS = 0 V; VDS = 25 V;
f = 1 MHz; Figure 12
VDD = 30 V; RL = 1.2 Ω;
VGS = 5 V; RG = 10 Ω
from drain lead 6 mm from
package to centre of die
from contact screw on
mounting base to centre of
die SOT78
from upper edge of drain
mounting base to centre of
die SOT404 / SOT226
Ls internal source inductance from source lead to source
bond pad
9397 750 08649
Product data
Rev. 01 — 24 October 2001
Min
40
36
1
0.5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ Max Unit
--V
--V
1.5 2
--
- 2.3
0.05 10
- 500
2 100
V
V
V
µA
µA
nA
3.5
-
3.7
2.9
128
13
56
6200
1040
680
62
309
365
306
4.5
3.5
4.4
8.3
5.9
4
-
-
-
8260
1250
940
-
-
-
-
-
-
mΩ
mΩ
mΩ
mΩ
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
nH
nH
2.5 -
nH
7.5 -
nH
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
5 of 15
5 Page 
Philips Semiconductors
BUK95/96/9E04-40A
TrenchMOS™ logic level FET
Plastic single-ended package; low-profile 3 lead TO-220AB
SOT226
D1 E
D
L2
b1
L
L1
123
ee
b
A
A1
mounting
base
Q
c
0 5 10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A A1 b b1 c
D D1 E
e
L
L1
L2(1)
max
Q
mm
4.5 1.40 0.9
4.1 1.27 0.7
1.3 0.7
1.0 0.4
9.65
8.65
1.5
1.1
10.3
9.7
2.54
15.0
13.5
3.30
2.79
3.0
2.6
2.2
Note
1. Terminals in this zone are not tinned.
OUTLINE
VERSION
SOT226
REFERENCES
IEC
JEDEC
EIAJ
low-profile
3-lead TO-220AB
EUROPEAN
PROJECTION
ISSUE DATE
99-05-27
99-09-13
Fig 18. SOT226 (I2-PAK).
9397 750 08649
Product data
Rev. 01 — 24 October 2001
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
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