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25L3205D PDF 데이터시트 ( Data , Function )

부품번호 25L3205D 기능
기능 MX25L3205D
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25L3205D 데이터시트, 핀배열, 회로
MX25L1605D
MX25L3205D
MX25L6405D
FEATURES
16M-BIT [x 1 / x 2] CMOS SERIAL FLASH
32M-BIT [x 1 / x 2] CMOS SERIAL FLASH
64M-BIT [x 1 / x 2] CMOS SERIAL FLASH
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
16M:16,777,216 x 1 bit structure or 8,388,608 x 2 bits (two I/O read mode) structure
32M:33,554,432 x 1 bit structure or 16,772,216 x 2 bits (two I/O read mode) structure
64M:67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two I/O read mode) structure
• 512 Equal Sectors with 4K byte each (16Mb)
1024 Equal Sectors with 4K byte each (32Mb)
2048 Equal Sectors with 4K byte each (64Mb)
- Any Sector can be erased individually
• 32 Equal Blocks with 64K byte each (16Mb)
64 Equal Blocks with 64K byte each (32Mb)
128 Equal Blocks with 64K byte each (64Mb)
- Any Block can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
• High Performance
- Fast access time: 86MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock (30pF + 1TTL Load)
- Serial clock of two I/O read mode : 50MHz (15pF + TTL Load), which is equivalent to 100MHz
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Byte program time: 9us (typical)
- Continuously program mode (automatically increase address under word program mode)
- Fast erase time: 60ms(typ.) /sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 14s(typ.) /chip for
16Mb, 25s(typ.) for 32Mb, and 50s(typ.) for 64Mb
• Low Power Consumption
- Low active read current: 25mA(max.) at 86MHz, 20mA(max.) at 66MHz and 10mA(max.) at 33MHz
- Low active programming current: 20mA (max.)
- Low active erase current: 20mA (max.)
- Low standby current: 20uA (max.)
- Deep power-down mode 1uA (typical)
• Typical 100,000 erase/program cycles
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions
- Additional 512-bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
P/N: PM1290
1 REV. 1.4, OCT. 01, 2008




25L3205D pdf, 반도체, 판매, 대치품
PIN CONFIGURATIONS
16-PIN SOP (300mil)
HOLD#
VCC
NC
NC
NC
NC
CS#
SO/SIO1
1
2
3
4
5
6
7
8
16 SCLK
15 SI/SIO0
14 NC
13 NC
12 NC
11 NC
10 GND
9 WP#/ACC
MX25L1605D
MX25L3205D
MX25L6405D
8-PIN SOP (200mil, 150mil)
CS#
SO/SIO1
WP#/ACC
GND
1
2
3
4
8 VCC
7 HOLD#
6 SCLK
5 SI/SIO0
8-LAND WSON (8x6mm, 6x5mm), USON (4x4mm)
CS#
SO/SIO1
WP#/ACC
GND
1
2
3
4
8 VCC
7 HOLD#
6 SCLK
5 SI/SIO0
8-PIN PDIP (300mil)
CS#
SO/SIO1
WP#/ACC
GND
1
2
3
4
8 VCC
7 HOLD#
6 SCLK
5 SI/SIO0
PACKAGE OPTIONS
150mil 8-SOP
200mil 8-SOP
300mil 16-SOP
300mil 8-PDIP
6x5mm WSON
8x6mm WSON
4x4mm USON
16M
V
V
V
V
V
V
32M 64M
V
VV
V
V
V
V
PIN DESCRIPTION
SYMBOL
CS#
SI/SIO0
SO/SIO1
SCLK
WP#/ACC
HOLD#
VCC
GND
DESCRIPTION
Chip Select
Serial Data Input (for 1 x I/O)/ Serial Data
Input & Output (for 2xI/O read mode)
Serial Data Output (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O read mode)
Clock Input
Write protection: connect to GND ;
9.5~10.5V for program/erase
acceleration: connect to 9.5~10.5V
Hold, to pause the device without
deselecting the device
+ 3.3V Power Supply
Ground
P/N: PM1290
REV. 1.4, OCT. 01, 2008
4

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25L3205D 전자부품, 판매, 대치품
MX25L1605D
MX25L3205D
MX25L6405D
Table 2. Protected Area Sizes
Status bit
BP3 BP2 BP1 BP0
00 0 0
00 0 1
00 1 0
00 1 1
01 0 0
01 0 1
01 1 0
01 1 1
10 0 0
10 0 1
10 1 0
10 1 1
11 0 0
11 0 1
11 1 0
11 1 1
16Mb
0(none)
1(1block, block 31th)
2(2blocks, block 30th-31th)
3(4blocks, block 28th-31th)
4(8blocks, block 24th-31th)
5(16blocks, block 16th-31th)
6(32blocks, all)
7(32blocks, all)
8(32blocks, all)
9(32blocks, all)
10(16blocks, block 0th-15th)
11(24blocks, block 0th-23th)
12(28blocks, block 0th-27th)
13(30blocks, block 0th-29th)
14(31blocks, block 0th-30th)
15(32blocks, all)
Protect Level
32Mb
0(none)
1(1block, block 63th)
2(2blocks, block 62th-63th)
3(4blocks, block 60th-63th)
4(8blocks, block 56th-63th)
5(16blocks, block 48th-63th)
6(32blocks, block 32th-63th)
7(64blocks, all)
8(64blocks, all)
9(32blocks, block 0th-31th)
10(48blocks, block 0th-47th)
11(56blocks, block 0th-55th)
12(60blocks, block 0th-59th)
13(62blocks, block 0th-61th)
14(63blocks, block 0th-62th)
15(64blocks, all)
64Mb
0(none)
1(2blocks, block 126th-127th)
2(4blocks, block 124th-127th)
3(8blocks, block 120th-127th)
4(16blocks, block 112th-127th)
5(32blocks, block 96th-127th)
6(64blocks,block 64th-127th)
7(128blocks, all)
8(128blocks, all)
9(64blocks, block 0th-63th)
10(96blocks, block 0th-95th)
11(112blocks, block 0th-111th)
12(120blocks, block 0th-119th)
13(124blocks, block 0th-123th)
14(126blocks, block 0th-125th)
15(128blocks, all)
II. Additional 512-bit secured OTP for unique identifier: to provide 512-bit one-time program area for setting device
unique serial number - Which may be set by factory or system customer. Please refer to table 3. 512-bit secured OTP
definition.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 512-bit secured OTP by entering 512-bit secured OTP mode (with ENSO command), and going through
normal program procedure, and then exiting 512-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) command
to set customer lock-down bit1 as "1". Please refer to table of "security register definition" for security register bit
definition and table of "512-bit secured OTP definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 512-bit secured OTP
mode, array access is not allowed.
Table 3. 512-bit Secured OTP Definition
Address range
Size
xxxx00~xxxx0F
128-bit
Standard
Factory Lock
ESN (electrical serial number)
xxxx10~xxxx3F
384-bit
N/A
Customer Lock
Determined by customer
P/N: PM1290
REV. 1.4, OCT. 01, 2008
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25L3205

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25L3205D

MX25L3205D

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