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ATF22V10CQ 데이터시트 PDF




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부품번호 ATF22V10CQ 기능
기능 High-performance Electrically Erasable Programmable Logic Device
제조업체 ATMEL Corporation
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ATF22V10CQ 데이터시트, 핀배열, 회로
Features
Industry-standard Architecture
– Low-cost, Easy-to-use Software Tools
High-speed, Electrically Erasable Programmable Logic Devices
– 5ns Maximum Pin-to-pin Delay
Latch Feature Holds Inputs to Previous Logic States
Pin-controlled Standby Power (10µA Typical)
Advanced Flash Technology
– Reprogrammable
– 100% Tested
High-reliability CMOS Process
– 20-year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200mA Latch-up Immunity
Dual Inline and Surface Mount Packages in Standard Pinouts
PCI-compliant
Green Package Options (Pb/Halide-free/RoHS Compliant) Available
Full Military, Commercial and Industrial Temperature Ranges
Backward-Compatible with Atmel ATF22V10B(Q) and Atmel AT22V10(L)
Applications Include Glue Logic for 5.0V Systems, DMA Control, State Machine
Control, Graphics Processing
High-performance
Electrically
Erasable
Programmable
Logic Device
Atmel ATF22V10C
Atmel ATF22V10CQ
1. Description
The Atmel® ATF22V10C is a high-performance CMOS (electrically erasable) pro-
grammable logic device (PLD) that utilizes proven electrically erasable Flash memory
technology from Atmel. Speeds down to 5ns and power dissipation as low as 10µA
(typical) are offered. All speed ranges are specified over the full 5V ± 10% range for
military and industrial temperature ranges, and 5V ± 5% for commercial temperature
ranges.
Several low-power options allow selection of the best solution for various types of
power-limited applications. Each of these options significantly reduces total system
power and enhances system reliability.
See separate datasheet for
the Atmel ATF22V10C(Q)Z
0735U–PLD–7/10




ATF22V10CQ pdf, 반도체, 판매, 대치품
4.1 DC Characteristics
Symbol Parameter
Condition
Min Typ
Max
IIL
Input or I/O Low
Leakage Current
0 VIN VIL (Max)
-10.0
IIH
Input or I/O High
Leakage Current
3.5 VIN VCC
10.0
ICC
Power Supply Current,
Standby
VCC = Max,
VIN = Max,
Outputs Open
C-5, 7, 10
C-10
C-15
CQ-15
Com.
Ind.
Ind.
Ind.
85.0 130.0
90.0 140.0
65.0 115.0
35.0 70.0
C-5, 7, 10 Com.
150.0
C-10
ICC2
Clocked Power Supply
Current
VCC = Max, Outputs Open,
f = 15MHz
C-15
C-15
Ind., Mil.
Ind.
Mil.
160.0
70.0 125
160.0
CQ-15
Ind.
40.0 80.0
IPD
IOS(1)
Power Supply Current,
PD Mode
Output Short Circuit
Current
VCC = Max
VIN = 0, Max
VOUT = 0.5V
Com.
Ind.
10.0 500.0
10.0 650.0
-130.0
VIL
VIH
VOL
VOH
Note:
Input Low Voltage
-0.5 0.8
Input High Voltage
2.0 VCC+0.75
Output Low Voltage
VIN = VIH or VIL,
VCC = Min
IOL = 16mA
IOL = 12mA
Com., Ind.
Mil.
0.5
0.5
Output High Voltage
VIN = VIH or VIL,
VCC = Min
IOH = -4.0mA
2.4
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec
Units
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
mA
V
V
V
V
V
4.2 AC Waveforms (1)
CLOCK
Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified
4 Atmel ATF22V10C(Q)
0735U–PLD–7/10

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ATF22V10CQ 전자부품, 판매, 대치품
Atmel ATF22V10C(Q)
4.7 Power-up Reset
The registers in the Atmel® ATF22V10Cs are designed to reset during power-up. At a point delayed slightly from
VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the
output buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the following conditions are required:
1. The VCC rise must be monotonic, and starts below 0.7V
2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high
3. The clock must remain stable during tPR
Figure 4-1. Power-up Reset Timing
VRST
POWER
t PR
REGISTERED
OUTPUTS
tS
CLOCK
tW
4.8 Preload of Registered Outputs
The ATF22V10C registers are provided with circuitry to allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC
file preload sequence will be done automatically by most of the approved programmers after the programming.
5. Electronic Signature Word
There are 64-bits of programmable memory that are always available to the user, even if the device is secured.
These bits can be used for user-specific data.
6. Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF22V10C fuse patterns. Once programmed,
fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible.
The security fuse should be programmed last, as its effect is immediate.
7. Programming/Erasing
Programming/erasing is performed using standard PLD programmers. See “CMOS PLD Programming Hardware
and Software Support” for information on software/programming.
Table 7-1. Programming/Erasing
Parameter
tPR
VRST
Description
Power-up Reset Time
Power-up Reset Voltage
Typ Max Units
600 1,000
ns
3.8 4.5
V
0735U–PLD–7/10
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관련 데이터시트

부품번호상세설명 및 기능제조사
ATF22V10C

High-performance Electrically Erasable Programmable Logic Device

ATMEL Corporation
ATMEL Corporation
ATF22V10CQ

High-performance Electrically Erasable Programmable Logic Device

ATMEL Corporation
ATMEL Corporation

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