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PDF RTL8201EL-GR Data sheet ( Hoja de datos )
| Número de pieza | RTL8201EL-GR | |
| Descripción | SINGLE-CHIP/PORT 10/100 FAST ETHERNET PHYCEIVER | |
| Fabricantes | Realtek | |
| Logotipo |  |
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RTL8201E-GR
RTL8201EL-GR
RTL8201E-VB-GR
RTL8201EL-VB-GR
SINGLE-CHIP/PORT 10/100 FAST
ETHERNET PHYCEIVER WITH AUTO MDIX
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.3
16 December 2008
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
1 page  
RTL8201E(L)
Datasheet
List of Tables
TABLE 1. MII INTERFACE ..............................................................................................................................................................6
TABLE 2. RMII INTERFACE (RTL8201E(L)-VB ONLY) ................................................................................................................8
TABLE 3. SNI (SERIAL NETWORK INTERFACE) 10MBPS ONLY......................................................................................................8
TABLE 4. CLOCK INTERFACE .........................................................................................................................................................8
TABLE 5. 10MBPS/100MBPS NETWORK INTERFACE......................................................................................................................9
TABLE 6. DEVICE CONFIGURATION INTERFACE.............................................................................................................................9
TABLE 7. LED INTERFACE/PHY ADDRESS CONFIGURATION ......................................................................................................10
TABLE 8. POWER AND GROUND PINS ..........................................................................................................................................10
TABLE 9. RESET AND OTHER PINS...............................................................................................................................................10
TABLE 10. NC (NOT CONNECTED) PINS........................................................................................................................................10
TABLE 11. REGISTER 0 BASIC MODE CONTROL REGISTER............................................................................................................11
TABLE 12. REGISTER 1 BASIC MODE STATUS REGISTER...............................................................................................................12
TABLE 13. REGISTER 2 PHY IDENTIFIER REGISTER 1 ...................................................................................................................12
TABLE 14. REGISTER 3 PHY IDENTIFIER REGISTER 2 ...................................................................................................................13
TABLE 15. REGISTER 4 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) .....................................................................13
TABLE 16. REGISTER 5 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR)......................................................14
TABLE 17. REGISTER 6 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) ..............................................................................15
TABLE 18. REGISTER 16 NWAY SETUP REGISTER (NSR) .............................................................................................................15
TABLE 19. REGISTER 17 LOOPBACK, BYPASS, RECEIVER ERROR MASK REGISTER (LBREMR)...................................................15
TABLE 20. REGISTER 18 RX_ER COUNTER (REC) .......................................................................................................................16
TABLE 21. REGISTER 19 SNR DISPLAY REGISTER ........................................................................................................................16
TABLE 22. REGISTER 25 TEST REGISTER.......................................................................................................................................16
TABLE 23. SERIAL MANAGEMENT ................................................................................................................................................19
TABLE 24. SETTING THE MEDIUM TYPE AND INTERFACE MODE TO MAC ....................................................................................20
TABLE 25. AUTO-NEGOTIATION MODE PIN SETTINGS ..................................................................................................................21
TABLE 26. POWER SAVING MODE PIN SETTINGS ..........................................................................................................................22
TABLE 27. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................26
TABLE 28. OPERATING CONDITIONS .............................................................................................................................................26
TABLE 29. POWER ON SEQUENCE .................................................................................................................................................26
TABLE 30. PHY RESET SEQUENCE OPERATING CONDITIONS........................................................................................................27
TABLE 31. POWER DISSIPATION....................................................................................................................................................27
TABLE 32. INPUT VOLTAGE: VCC .................................................................................................................................................28
TABLE 33. MII TRANSMISSION CYCLE TIMING .............................................................................................................................28
TABLE 34. MII RECEPTION CYCLE TIMING ...................................................................................................................................30
TABLE 35. RMII TRANSMISSION CYCLE TIMING (RTL8201E(L)-VB ONLY) ...............................................................................31
TABLE 36. RMII RECEPTION CYCLE TIMING (RTL8201E(L)-VB ONLY) .....................................................................................31
TABLE 37. SNI TRANSMISSION CYCLE TIMING.............................................................................................................................32
TABLE 38. SNI RECEPTION CYCLE TIMING...................................................................................................................................33
TABLE 39. MDC/MDIO TIMING ...................................................................................................................................................34
TABLE 40. CRYSTAL CHARACTERISTICS .......................................................................................................................................35
TABLE 41. TRANSFORMER CHARACTERISTICS ..............................................................................................................................35
TABLE 42. ORDERING INFORMATION ............................................................................................................................................38
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
v
Track ID: JATR-1076-21 Rev. 1.3
5 Page 
5.3. RTL8201E QFN-32 Pin Assignments
RTL8201E(L)
Datasheet
Figure 3. RTL8201E QFN-32 Pin Assignment
5.4. Green Package and Version Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 3. The version is shown in the
location marked ‘V’.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
5
Track ID: JATR-1076-21 Rev. 1.3
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet RTL8201EL-GR.PDF ] | |
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