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PDF PALLV22V10Z-25 Data sheet ( Hoja de datos )
| Número de pieza | PALLV22V10Z-25 | |
| Descripción | Zero-Power 24-Pin EE CMOS Versatile PAL Device | |
| Fabricantes | Advanced Micro Devices | |
| Logotipo |  |
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FINAL
IND: -25
PALLV22V10Z-25
Low-Voltage, Zero-Power 24-Pin EE CMOS Versatile
PAL Device
DISTINCTIVE CHARACTERISTICS
s Low-voltage operation, 3.3 V JEDEC
compatible
s Zero-power CMOS technology
— 30 µA standby current
— 25-ns propagation delay (tPD)
s Unused product term disable for reduced
power consumption
s Industrial operating conditions
— TA = –40°C to +85°C
s 3.3-V (CMOS) and 5-V (CMOS and TTL)
compatible inputs and I/O
s Electrically-erasable technology provides
reconfigurable logic and full testability
GENERAL DESCRIPTION
The PALLV22V10Z is an advanced PAL device built
with low-voltage, zero-power, electrically-erasable
CMOS technology. It provides user-programmable logic
for replacing conventional zero-power CMOS SSI/MSI
gates and flip-flops at a reduced chip count.
The PALLV22V10Z provides low voltage and zero
standby power. At 30 µA maximum standby current, the
PALLV22V10Z allows battery powered operation for an
extended period.
The ZPAL device implements the familiar Boolean logic
transfer function, the sum of products. The PAL device
is a programmable AND array driving a fixed OR array.
The AND array is programmed to create custom product
terms, while the OR array sums selected terms at the
outputs.
The product terms are connected to the fixed OR array
with a varied distribution from 8 to16 across the outputs
s 10 macrocells programmable as registered or
combinatorial, and active high or active low to
match application needs
s Varied product term distribution allows up to
16 product terms per output for complex
functions
s Global asynchronous reset and synchronous
preset for initialization
s Power-up reset for initialization and register
preload for testability
s Extensive third-party software and programmer
support through FusionPLD partners
s 24-pin SKINNYDIP and 28-pin PLCC packages
save space
(see Block Diagram). The OR sum of the products feeds
the output macrocell. Each macrocell can be pro-
grammed as registered or combinatorial, and active
high or active low. The output configuration is deter-
mined by two bits controlling two multiplexers in each
macrocell.
AMD’s FusionPLD program allows PALLV22V10Z de-
signs to be implemented using a wide variety of popular
industry-standard design tools. By working closely with
the FusionPLD partners, AMD certifies that the tools
provide accurate, quality support. By ensuring that third-
party tools are available, costs are lowered because a
designer does not have to buy a complete set of new
tools for each device. The FusionPLD program also
greatly reduces design time since a designer can use a
tool that is already installed and familiar.
Publication# 17661 Rev. D Amendment /0
Issue Date: February 1996
2-261
1 page  
AMD
AR
DQ
CLK Q
SP
S0 = 0
S1 = 0
S0 = 0
S1 = 1
Registered/Active Low
AR
DQ
CLK Q
SP
S0 = 1
S1 = 0
Combinatorial/Active Low
S0 = 1
S1 = 1
Registered/Active High
Combinatorial/Active High
Figure 2. Macrocell Configuration Options
17661D-5
Programmable Three-State Outputs
Each output has a three-state output buffer with three-
state control. A product term controls the buffer, allow-
ing enable and disable to be a function of any product of
device inputs or output feedback. The combinatorial
output provides a bidirectional I/O pin, and may be con-
figured as a dedicated input if the buffer is always
disabled.
Programmable Output Polarity
The polarity of each macrocell output can be active high
or active low, either to match output signal needs or to
reduce product terms. Programmable polarity allows
Boolean expressions to be written in their most compact
form (true or inverted), and the output can still be of the
desired polarity. It can also save “DeMorganizing”
efforts.
Selection is controlled by programmable bit S0 in the
output macrocell, and affects both registered and com-
binatorial outputs. Selection is automatic, based on the
design specification and pin definitions. If the pin defini-
tion and output equation have the same polarity, the out-
put is programmed to be active high (S0 = 1).
Preset/Reset
For initialization, the PALLV22V10Z has additional
Preset and Reset product terms. These terms are con-
nected to all registered outputs. When the Synchronous
Preset (SP) product term is asserted high, the output
registers will be loaded with a HIGH on the next LOW-to-
HIGH clock transition. When the Asynchronous Reset
(AR) product term is asserted high, the output registers
will be immediately loaded with a LOW independent of
the clock.
Note that preset and reset control the flip-flop, not the
output pin. The output level is determined by the output
polarity selected.
Benefits of Lower Operating Voltage
The PALLV22V10Z has an operating voltage range of
3.0 V to 3.6 V. Low voltage allows for lower operating
power consumption, longer battery life, and/or smaller
batteries for notebook applications. The PALLV22V10Z
inputs accept voltages up to 5.5 V, so they are safe for
mixed voltage design.
Because power is proportional to the square of the volt-
age, reduction of the supply voltage from 5.0 V to 3.3 V
significantly reduces power consumption. This directly
translates to longer battery life for portable applications.
Lower power consumption can also be used to reduce
the size and weight of the battery. Thus, 3.3 V designs
facilitate a reduction in the form factor.
A lower operating voltage results in a reduction of I/O
voltage swings. This reduces noise generation and pro-
vides a less hostile environment for board design. Lower
operating voltage also reduces electromagnetic radia-
tion noise and makes obtaining FCC approval easier.
PALLV22V10Z-25
2-265
5 Page 
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
Must be
Steady
May
Change
from H to L
May
Change
from L to H
Don’t Care,
Any Change
Permitted
Does Not
Apply
OUTPUTS
Will be
Steady
Will be
Changing
from H to L
Will be
Changing
from L to H
Changing,
State
Unknown
Center
Line is High-
Impedance
“Off” State
KS000010-PAL
SWITCHING TEST CIRCUIT
VCC
AMD
S1
Output
R1
Test Point
R2 CL
S2
17661D-13
Specification
tPD, tCO
tEA
tER
S1
Closed
Z → H: Open
Z → L: Closed
H → Z: Open
L → Z: Closed
S2
Closed
Z → H: Closed
Z → L: Open
H → Z: Closed
L → Z: Open
CL R1
R2
30 pF 1.6K Ω 1.6K Ω
5 pF
Measured
Output Value
VCC/2
VCC/2
H → Z: VOH – 0.5 V
L → Z: VOL + 0.5 V
PALLV22V10Z-25
2-271
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet PALLV22V10Z-25.PDF ] | |
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