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PDF ASD5020L640INT Data sheet ( Hoja de datos )
| Número de pieza | ASD5020L640INT | |
| Descripción | High Speed Mode Multi-Mode 12-bit 640 MSPS / 8-bit 1000 MSPS Analog to Digital Converter | |
| Fabricantes | Arctic Silicon Devices | |
| Logotipo |  |
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Preliminary Product Specification
ASD5020 High Speed Mode
Multi-Mode 12-bit 640 MSPS / 8-bit 1000 MSPS Analog to Digital Converter
Features
● 12-bit Modes
● Single Channel Mode: FSmax = 640 MSPS
● Dual Channel Mode: FSmax = 320 MSPS
● Quad Channel Mode: FSmax = 160 MSPS
● SNR: 71 dB, SFDR: 65 dB
● 8-bit Modes
● Single Channel Mode: FSmax = 1000 MSPS
● Dual Channel Mode: FSmax = 500 MSPS
● Quad Channel Mode: FSmax = 250 MSPS
● SNR: 49 dB, SFDR: 65 dB
● Integrated Cross Point Switches with instantaneous
switching
● Internal low jitter programmable Clock Divider
● Ultra Low Power Dissipation
● 490mW including I/O at 640 MSPS
● 0.5 µs start-up time from Sleep, 15 µs from Power
Down
● Internal reference circuitry with no external
components required
● Coarse and fine gain control
● Digital fine gain adjustment for each ADC
● Internal offset correction
● 1.8 V supply voltage
● 1.7 - 3.6 V CMOS logic on control interface pins
● Serial LVDS/RSDS output
● 12, 14, 16 and Dual 8-bit modes available
● 7mm x 7mm 48 QFN Package
Description
The ASD5020 is a versatile high performance low power
analog-to-digital converter (ADC), utilizing time-interleaving
to increase sampling rate. Integrated Cross Point Switches
activate the input selected by the user.
In single channel mode, one of the four inputs can be
selected as valid input to the single ADC channel. In dual
channel mode, any two of the four inputs can be selected to
each ADC channel. In quad channel mode, any input can be
assigned to any ADC channel.
An internal, low jitter and programmable clock divider makes
it possible to use a single clock source for all operational
modes.
The ASD5020 is based on a proprietary structure, and
employs internal reference circuitry, a serial control interface
and a serial LVDS output data. Data and frame
synchronization clocks are supplied for data capture at the
receiver. Internal digital fine gain can be set separately for
each ADC to calibrate for gain errors.
Various modes and configuration settings can be applied to
the ADC through the serial control interface (SPI). Each
channel can be powered down independently and output
data format can be selected through this interface. A full chip
idle mode can be set by a single external pin. Register
settings determine the exact function of this pin.
ASD5020 is designed to interface easily with Field
Programmable Gate Arrays (FPGAs) from several vendors.
Applications
● Precision Oscilloscopes
● Diversity Receivers
● Hi-End Ultrasound
● Communication Testing
● Non Destructive Testing
Serial control
interface
Clock
Divide
1/2/4/8
Interleave
PLL
LVDS
FCLKP
FCLKN
LCLKP
LCLKN
IP1 ADC 1
IN1
Digital
gain
LVDS
DP1A
DN1A
DP1B
DN1B
IP2 ADC 2
IN2
IP3
ADC 3
IN3
Digital
gain
Digital
gain
LVDS
LVDS
DP2A
DN2A
DP2B
DN2B
DP3A
DN3A
DP3B
DN3B
IP4 ADC 4
IN4
Digital
gain
LVDS
DP4A
DN4A
DP4B
DN4B
Figure 1: Functional Block Diagram
Vestre Rosten 81, 7075 Tiller, Norway
Phone: +47 73 10 29 00, Fax: +47 73 10 29 19
Page 1 of 34
Org. No: NO 991 265 163MVA
www.arcticsilicon.com
1 page  
Preliminary Product Specification
ASD5020 High Speed Mode
AVDD=DVDD=OVDD=1.8V, 50% clock duty cycle, -1dBFS 70 MHz input signal, Gain = 1X, 12-bit output, RSDS output data levels, unless
otherwise noted
Parameter
Description
Performance
SNR
Signal to Noise Ratio
Single Channel Mode , FS = 640 MSPS
Single Channel Mode , FS = 640 MSPS Gain = 10X
Dual Channel Mode , FS = 320 MSPS
Quad Channel Mode , FS = 160 MSPS
SINAD
Signal to Noise and Distortion Ratio
Single Channel Mode , FS = 640 MSPS
Single Channel Mode , FS = 640 MSPS, Gain = 10X
Dual Channel Mode , FS = 320 MSPS
Quad Channel Mode , FS = 160 MSPS
SFDR
Spurious Free Dynamic Range
Single Channel Mode , FS = 640 MSPS
Dual Channel Mode , FS = 320 MSPS
Quad Channel Mode , FS = 160 MSPS
ENOB
Effective number of Bits
Single Channel Mode , FS = 640 MSPS
Single Channel Mode , FS = 640 MSPS, Gain = 10X
Dual Channel Mode , FS = 320 MSPS
Quad Channel Mode , FS = 160 MSPS
Xtlk,HS2
CrossTalk Dual Ch Mode. Signal applied to 1 channel (FIN0). Measurement
taken on one channel with full scale at FIN1. FIN1 = 8 MHz, FIN0 = 9.9 MHz
Xtlk,HS4
CrossTalk Quad Ch Mode. Signal applied to 1 channel (FIN0). Measurement
taken on one channel with full scale at FIN1. FIN1 = 8 MHz, FIN0 = 9.9 MHz
Power
Supply
Single Ch: FS = 640 MSPS, Dual Ch: FS = 320 MSPS, Quad Ch: FS = 160
MSPS.
IAVDD
Analog Supply Current
IDVDD
Digital and output driver Supply Current
PAVDD
Analog Power
PDVDD
Digital Power
PTOT
Total Power Dissipation
PPD Power Down Mode Dissipation
PSLP
Deep Sleep Mode Power Dissipation
PSLPCH
Power Dissipation with all channels in sleep channel mode (Light Sleep)
PSLPCH_SAV Power Dissipation savings per channel off
Clock Inputs
FSmax
Max. Conversion Rate in Modes:
Single / Dual /
Quad Channel
FSmin
Min. Conversion Rate in Modes:
Single / Dual /
Quad Channel
Min Typ Max Unit
70 dBFS
52 dBFS
70 dBFS
70 dBFS
62 dBFS
51 dBFS
66 dBFS
67 dBFS
65 dBc
65 dBc
65 dBc
10.0 bits
8.0 bits
10.6 bits
10.8 bits
TBD dBc
TBD dBc
190 mA
82 mA
342 mW
148 mW
490 mW
15 µW
66 mW
121 mW
92 mW
640 / 320 /
160
MSPS
120 / 60 / MSPS
30
ASD5020
rev 2.0, 2010.11.08
Page 5 of 34
High Speed Mode
5 Page 
Preliminary Product Specification
Timing Diagrams
N+31
Analog input
N+32
N+33
N+35
N+34
Input clock
TLVDS
LCLKP
LCLKN
FCLKN
FCLKP
DxnA
D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
N-4 N-4 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N N N N N N N N N N N
DxnB
D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
N-3 N-3 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N+1 N+1 N+1 N+1 N+1 N+1 N+1 N+1 N+1 N+1 N+1
TP RO P
Figure 5: Quad channel - LVDS timing 12-bit output
N+62
Analog input
N+63
N+64
N+65
N+66
N+67
N+68
N+69
N+70
Input clock
LCLKP
LCLKN
FCLKN
FCLKP
TLVDS
Dx1A / Dx3A
D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0
N-8 N-8 N-4 N-4 N-4 N-4 N-4 N-4 N-4 N-4 N-4 N-4 N-4 N-4 N
D1
N
D2
N
D3
N
D4
N
D5
N
D6
N
D7
N
D8
N
D9
N
D10
N
Dx1B / Dx3B
D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
N-7 N-7 N-3 N-3 N-3 N-3 N-3 N-3 N-3 N-3 N-3 N-3 N-3 N-3 N+1 N+1 N+1 N+1 N+1 N+1 N+1 N+1 N+1 N+1 N+1
Dx2A / Dx4A
D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
N-6 N-6 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N+2 N+2 N+2 N+2 N+2 N+2 N+2 N+2 N+2 N+2 N+2
Dx2B / Dx4B
D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
N-5 N-5 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N+3 N+3 N+3 N+3 N+3 N+3 N+3 N+3 N+3 N+3 N+3
TP RO P
Figure 6: Dual channel - LVDS timing 12-bit output
ASD5020
rev 2.0, 2010.11.08
Page 11 of 34
High Speed Mode
11 Page | ||
| Páginas | Total 34 Páginas | |
| PDF Descargar | [ Datasheet ASD5020L640INT.PDF ] | |
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