Datasheet.kr   

XP2 데이터시트 PDF




Lattice Semiconductor에서 제조한 전자 부품 XP2은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 XP2 자료 제공

부품번호 XP2 기능
기능 FPGA fabric
제조업체 Lattice Semiconductor
로고 Lattice Semiconductor 로고


XP2 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 30 페이지수

미리보기를 사용할 수 없습니다

XP2 데이터시트, 핀배열, 회로
LatticeXP2™ Family Data Sheet
DS1009 Version 01.8, January 2012




XP2 pdf, 반도체, 판매, 대치품
LatticeXP2 Family Data Sheet
Architecture
January 2012
Data Sheet DS1009
Architecture Overview
Each LatticeXP2 device contains an array of logic blocks surrounded by Programmable I/O Cells (PIC). Inter-
spersed between the rows of logic blocks are rows of sysMEM™ Embedded Block RAM (EBR) and a row of sys-
DSP™ Digital Signal Processing blocks as shown in Figure 2-1.
On the left and right sides of the Programmable Functional Unit (PFU) array, there are Non-volatile Memory Blocks.
In configuration mode the nonvolatile memory is programmed via the IEEE 1149.1 TAP port or the sysCONFIG™
peripheral port. On power up, the configuration data is transferred from the Non-volatile Memory Blocks to the con-
figuration SRAM. With this technology, expensive external configuration memory is not required, and designs are
secured from unauthorized read-back. This transfer of data from non-volatile memory to configuration SRAM via
wide busses happens in microseconds, providing an “instant-on” capability that allows easy interfacing in many
applications. LatticeXP2 devices can also transfer data from the sysMEM EBR blocks to the Non-volatile Memory
Blocks at user request.
There are two kinds of logic blocks, the PFU and the PFU without RAM (PFF). The PFU contains the building
blocks for logic, arithmetic, RAM and ROM functions. The PFF block contains building blocks for logic, arithmetic
and ROM functions. Both PFU and PFF blocks are optimized for flexibility allowing complex designs to be imple-
mented quickly and efficiently. Logic Blocks are arranged in a two-dimensional array. Only one type of block is used
per row.
LatticeXP2 devices contain one or more rows of sysMEM EBR blocks. sysMEM EBRs are large dedicated 18Kbit
memory blocks. Each sysMEM block can be configured in a variety of depths and widths of RAM or ROM. In addi-
tion, LatticeXP2 devices contain up to two rows of DSP Blocks. Each DSP block has multipliers and adder/accumu-
lators, which are the building blocks for complex signal processing capabilities.
Each PIC block encompasses two PIOs (PIO pairs) with their respective sysIO buffers. The sysIO buffers of the
LatticeXP2 devices are arranged into eight banks, allowing the implementation of a wide variety of I/O standards.
PIO pairs on the left and right edges of the device can be configured as LVDS transmit/receive pairs. The PIC logic
also includes pre-engineered support to aid in the implementation of high speed source synchronous standards
such as 7:1 LVDS interfaces, found in many display applications, and memory interfaces including DDR and DDR2.
Other blocks provided include PLLs and configuration functions. The LatticeXP2 architecture provides up to four
General Purpose PLLs (GPLL) per device. The GPLL blocks are located in the corners of the device.
The configuration block that supports features such as configuration bit-stream de-encryption, transparent updates
and dual boot support is located between banks two and three. Every device in the LatticeXP2 family supports a
sysCONFIG port, muxed with bank seven I/Os, which supports serial device configuration. A JTAG port is provided
between banks two and three.
This family also provides an on-chip oscillator. LatticeXP2 devices use 1.2V as their core voltage.
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
2-1 DS1009 Architecture_01.5

4페이지










XP2 전자부품, 판매, 대치품
Lattice Semiconductor
Figure 2-3. Slice Diagram
FXB
FXA
A1
B1
C1
D1
From
Routing
M1
M0
A0
B0
C0
D0
Architecture
LatticeXP2 Family Data Sheet
FCO from Slice/PFU, FCI into Different Slice/PFU
CO F/SUM
LUT4 &
CARRY*
CI
LUT5
Mux
CO
LUT4 &
CARRY* F/SUM
CI
SLICE
D
FF*
OFX1
F1
Q1
To
Routing
OFX0
D
FF*
F0
Q0
CE
CLK
LSR
* Not in Slice 3
FCI into Slice/PFU, FCO from Different Slice/PFU
For Slices 0 and 2, memory control signals are generated from Slice 1 as follows:
WCK is CLK
WRE is from LSR
DI[3:2] for Slice 2 and DI[1:0] for Slice 0 data
WAD [A:D] is a 4bit address from slice 1 LUT input
Table 2-2. Slice Signal Descriptions
Function
Type
Signal Names
Input
Data signal
A0, B0, C0, D0
Input
Data signal
A1, B1, C1, D1
Input
Multi-purpose
M0
Input
Multi-purpose
M1
Input
Control signal
CE
Input
Control signal
LSR
Input
Control signal
CLK
Input Inter-PFU signal
FCI
Input Inter-slice signal
FXA
Input Inter-slice signal
FXB
Output
Data signals
F0, F1
Output
Data signals
Q0, Q1
Output
Data signals
OFX0
Output
Data signals
OFX1
Output Inter-PFU signal
FCO
1. See Figure 2-3 for connection details.
2. Requires two PFUs.
Description
Inputs to LUT4
Inputs to LUT4
Multipurpose Input
Multipurpose Input
Clock Enable
Local Set/Reset
System Clock
Fast Carry-In1
Intermediate signal to generate LUT6 and LUT7
Intermediate signal to generate LUT6 and LUT7
LUT4 output register bypass signals
Register outputs
Output of a LUT5 MUX
Output of a LUT6, LUT7, LUT82 MUX depending on the slice
Slice 2 of each PFU is the fast carry chain output1
2-4

7페이지


구       성 총 30 페이지수
다운로드[ XP2.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
XP-G

LEDs

Cree
Cree
XP-G2

LEDs

Cree
Cree

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵