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G2237-208-041PTC1 데이터시트, 핀배열, 회로
June 25, 2002, Issue 2
Part Numbers
G2216-208-041PF B2 (SDSL 2B1Q)
G2214-208-041DF B2 (SDSL CAP)
G2237-208-041PT B2 (SHDSL/HDSL2)
G2237-208-041PT C1 (SHDSL/HDSL2)
XDSL2TM SDSL, HDSL2, or SHDSL - ILD2
Dual-Channel, Low Power, Programmable
Transceiver with Integrated Framer and Line Drivers
Data Sheet
Overview
The GlobespanVirata® XDSL2™ Digital Subscriber Line
(DSL) chip sets provide low power, high density solutions for
2-wire DSL equipment. These chip sets are fully
programmable and field upgradeable eliminating the risk of
product obsolescence and accelerating the time-to-market for
new network services. The GlobespanVirata® XDSL2™ DSL
chip sets are fully interoperable with multi-vendor DSL chip
set solutions. This interoperability enables dynamic
interworking of multiple vendor DSL solutions with the
capability to interoperate with products that conform to ANSI
and ETSI DSL standards.
GlobespanVirata’s unique hardware platform supports
multiple dual-channel applications including SDSL, HDSL2,
and SHDSL, using population options for optimization.
The XDSL2 DSL chip sets incorporate two DSL bit pumps
plus framing into a three-chip solution comprised of a dual-
channel digital signal processor (DSP) with built-in framer and
two Analog Front Ends each with an Integrated Line Driver
(ILD2).
The XDSL2 chip sets interface directly with off-the-shelf T1/
E1 transceivers and Nx64 multiplexing, eliminating the need
for a separate DSL framer to combine and format the two DSL
channels into a standard interface. GlobespanVirata’s DSL
XDSL2 chip sets deliver two channels of full duplex
transmission up to 2320 kb/s, depending on the application.
The high density XDSL2 dual-channel DSL chip sets are ideal
for CO applications, while single-channel versions with
integrated framer are also available for CPE applications.
Features
Dual-channel DSP with framer that fully integrates
2 separate DSL chips into a single device
Two AFEs, each with an integrated differential line driver
2B1Q, CAP, or PAM line codes
Supports dual-channel symmetric data rates of 144 kb/s
to 2320 kb/s (depending on the application)
Supports IDSL with optional data interface rates of
64 kb/s, 128 kb/s, and 144 kb/s
Offers physical layer interoperability with competitive solu-
tions
Glueless interface to popular microprocessors
Transmission compliant with ETSI TS 101 135, ITU-T
G.991.1, and ANSI TR-28 for single pair 2B1Q and CAP,
ANSI T1.418 for HDSL2 and ITU-T G.991.2 for SHDSL
Reference design compatible with Bellcore GR-1089, IEC
60950, UL 1950, ITU-T K.20 and K.21
Built-in framer provides easy access to EOC and indicator
bits (framing can be bypassed completely for 2-channel
independent operation)
Interfaces directly with off-the-shelf single-channel T1/E1
transceivers
ATM UTOPIA Level 1 and 2 interface
A single oscillator and hybrid topology supports all speeds
+3.3V and +5V power supplies
Customer Interface
TDATA (A/B)
TClock (A/B)
Frame Pulse (A/B)
RDATA (A/B)
Rclock (A/B)
Frame Pulse (A/B)
Dual
Channel
DSP
w/Framer
µ Processor Interface
ILD2
ILD2
Figure 1. Block Diagram of XDSL2™ DSP with Two Single-Channel ILD2s
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions
DO-009643-DS, Issue 2




G2237-208-041PTC1 pdf, 반도체, 판매, 대치품
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
June 25, 2002
Retrain
Data Mode
Abort
Power Up
InitXCVR_CS()
Power Up
Activities
Reset DSP
InitXCVR()
Idle Mode
SetParamXCVR()
Idle Mode
Set all
framer
options
Optional
SetParamFramer()
Idle Mode
DSP/Framer Interrupt Received
Optional
SStatusXCVR()
Power Up/
Reset DSP
Start Up
Activities
Host Processes GTI_ACTIVE
ExecuteXCVR()
GTI_COMPLETE_PASS
Data Mode
DETAIL A
DETAIL A:
IDLE
MODE
FAILED STARTUP
May occur anytime
before Data Mode.
BOOT
LOAD HANDSHAKE
(not timed)
TRAINING
FRAMER
SYNC*
DATA MODE
DSP INTERRUPTS
STARTUP MODE
FRAMER INTERRUPTS
* Only if PLL is enabled
Figure 2. Typical Transceiver Power Up/Start Up
Sequence
Transceiver Power Up Sequence
Figure 2 describes a typical sequence from power up to
DATA mode for a transceiver. After power is applied to
both the Host and the transceiver, the Host calls the
InitXCVR_CS() and InitXCVR() routines to
initialize transceiver variables and to initialize the DSP/
Framer.
Next, the Host calls the SetParamXCVR() routine to
set up the parameters that are appropriate for start up of
the transceiver.
The SetParamFramer() routine is called by the Host
to initialize framer options.
After setting up the transceiver parameters, the Host
calls the ExecuteXCVR() routine to execute the
command that was set up using the SetParamXCVR()
routine. With a successful completion of the
ExecuteXCVR() routine, the transceiver will now be in
DATA mode.
The SStatusXCVR() routine is used to track
performance and to obtain information from the
transceiver about what state the transceiver is in (i.e.,
monitor start-up, check signal quality, etc.).
Setting Up the Command Parameters
[SetParamXCVR()]
The routine SetParamXCVR() processes the
parameter array structure that will be executed when
the ExecuteXCVR() routine is called.
The parameter structure will be similar to the following
start-up example:
struct PARAM_XCVR_ARRAY Items;
Items.length = GTI_NUM_OF_CMD_PARAMETERS
Items.item[GTI_ACTION_ITEM]=GTI_STARTUP_REQ;
Items.item[GTI_MODE_ITEM]=GTI_CO;
Items.item[GTI_POWER_SCALE_ITEM]=GTI_DEFAULT_SCALE;
Items.item[GTI_FRAMER_TYPE_ITEM]= GTI_UTOPIA_L2;
.
.
.
GlobespanVirata, Inc. — Proprietary
4
Use pursuant to Company Instructions
DO-009643-DS, Issue 2

4페이지










G2237-208-041PTC1 전자부품, 판매, 대치품
June 25, 2002
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
Table 5. Typical HDSL2 System Power Consumption Per
Port (DSP/Framer in a 144 LPQ2)
Drain Current (mA)
Line Rate
Power/Port
(Kb/s)
3.3VD
DSP & ILD2
5VA ILD2
(mW)
T1
(1.552)
270
150 1681
NOTE:
1. Power per channel based on dual-channel
operation
2. Based on customer schematic:
G-02-2302-1006C-01 using 1:5.4 transformer
3. Transmit power: 16.8 dbm (nominal)
Table 6. Maximum Junction Temperature
TJ Maximum
125 oC
Table 7. Typical SHDSL System Power Consumption Per
Channel (DSP/Framer in a 144 LPQ2)
Line Rate
(Kb/s)
Drain Current (mA)
3.3VD
5VA
DSP & ILD2 ILD2
144
100.0
125.0
200
105.0
125.0
208
105.0
125.0
272
120.0
125.0
392
130.0
125.0
400
130.0
125.0
528
135.0
125.0
776
160.0
125.0
784
160.0
125.0
1040
180.0
125.0
1168
185.0
125.0
1552
225.0
130.0
2056
245.0
130.0
2064
245.0
130.0
2312
270.0
130.0
2320
270.0
130.0
Power/Port
(mW)
955.0
971.5
971.5
1021.0
1054.0
1054.0
1070.5
1153.0
1153.0
1219.0
1235.5
1392.5
1458.5
1458.5
1541.0
1541.0
NOTE:
1. Power per channel based on dual-channel
operation
2. Based on customer schematic:
G-02-2302-1006C-03 using 1:4 transformer
3. Transmit power: 13.5 dbm (nominal at all rates)
4. Measured during activation and data mode
5. All Nx64 payload rates are supported (where N =
3 through 36). The line rates listed in Table 7 are a
few typical data points
Electrical Interface Specification
All processor interfaces, customer clock and data, and
diagnostic interface inputs and outputs associated with
the 144-pin DSP Core are compatible with 5V CMOS
and TTL logic, as well as 3.3V CMOS logic. While the
DSP is a 3.3V device, all the above inputs are designed
to be 5V tolerant. The Control Interface supports
multiplexed, non-multiplexed, and Motorola processor
interface modes.
DO-009643-DS, Issue 2
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions
7

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