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PDF MFRC53001T Data sheet ( Hoja de datos )
| Número de pieza | MFRC53001T | |
| Descripción | Standard MIFARE reader solution | |
| Fabricantes | NXP Semiconductors | |
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MFRC530
Standard MIFARE reader solution
Rev. 3.4 — 12 February 2014
057434
Product data sheet
COMPANY PUBLIC
1. Introduction
This data sheet describes the functionality of the MFRC530 Integrated Circuit (IC). It
includes the functional and electrical specifications and from a system and hardware
viewpoint gives detailed information on how to design-in the device.
Remark: The MFRC530 supports all variants of the MIFARE Classic, MIFARE 1K and
MIFARE 4K RF identification protocols. To aid readability throughout this data sheet, the
MIFARE Classic, MIFARE 1K and MIFARE 4K products and protocols have the generic
name MIFARE.
2. General description
The MFRC530 is highly integrated reader IC for contactless communication at 13.56 MHz.
The MFRC530 reader IC provides:
• outstanding modulation and demodulation for passive contactless communication
• a wide range of methods and protocols
• pin compatibility with the CLRC632, MFRC500, MFRC531 and SLRC400
All protocol layers of the ISO/IEC 14443 A are supported
The receiver module provides a robust and efficient demodulation/decoding circuitry
implementation for compatible transponder signals (see Section 9.10 on page 31). The
digital module, manages the complete ISO/IEC 14443 A standard framing and error
detection (parity and CRC). In addition, it supports the fast Crypto1 security algorithm for
authenticating the MIFARE products (see Section 9.13 on page 37).
The internal transmitter module (Section 9.9 on page 28) can directly drive an antenna
designed for a proximity operating distance up to 100 mm without any additional active
circuitry.
A parallel interface can be directly connected to any 8-bit microprocessor to ensure
reader/terminal design flexibility. In addition, Serial Peripheral Interface (SPI) compatibility
is supported (see Section 9.1.4 on page 9).
1 page  
NXP Semiconductors
8. Pinning information
MFRC530
Standard MIFARE reader solution
OSCIN 1
IRQ 2
MFIN 3
MFOUT 4
TX1 5
TVDD 6
TX2 7
TVSS 8
NCS 9
NWR/R/NW/nWrite 10
NRD/NDS/nDStrb 11
DVSS 12
AD0/D0 13
AD1/D1 14
AD2/D2 15
AD3/D3 16
Fig 2. MFRC530 pin configuration
MFRC530
32 OSCOUT
31 RSTPD
30 VMID
29 RX
28 AVSS
27 AUX
26 AVDD
25 DVDD
24 A2
23 A1
22 A0/nWait
21 ALE/AS/nAStrb
20 D7/AD7
19 D6/AD6
18 D5/AD5
17 D4/AD4
001aam353
8.1 Pin description
Table 3.
Pin
1
Pin description
Symbol
Type[1]
OSCIN
I
2
3
4[2]
5
6
7
8
9
10[3]
11[3]
IRQ
MFIN
MFOUT
TX1
TVDD
TX2
TVSS
NCS
NWR
R/NW
nWrite
NRD
NDS
nDStrb
O
I
O
O
P
O
G
I
I
I
I
I
I
I
Description
oscillator/clock inputs:
crystal oscillator input to the oscillator’s inverting amplifier
externally generated clock input; fclk(ext) = 13.56 MHz
interrupt request: generates an output signaling an interrupt event
ISO/IEC 14443 A MIFARE serial data interface input
serial data ISO/IEC 14443 A output
transmitter 1 modulated carrier output; 13.56 MHz
transmitter power supply for the TX1 and TX2 output stages
transmitter 2 modulated carrier output; 13.56 MHz
transmitter ground for the TX1 and TX2 output stages
not chip select input is used to select and activate the MFRC530’s microprocessor
interface
not write input generates the strobe signal for writing data to the MFRC530
registers when applied to pins D0 to D7
read not write input is used to switch between read or write cycles
not write input selects the read or write cycle to be performed
not read input generates the strobe signal for reading data from the MFRC530
registers when applied to pins D0 to D7
not data strobe input generates the strobe signal for the read and write cycles
not data strobe input generates the strobe signal for the read and write cycles
MFRC530
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.4 — 12 February 2014
057434
© NXP B.V. 2014. All rights reserved.
5 of 115
5 Page 
NXP Semiconductors
MFRC530
Standard MIFARE reader solution
Table 8. SPI read address
Address
(MOSI)
Bit 7 Bit 6
(MSB)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)[1]
byte 0
1 address address address address address address reserved
byte 1 to byte n reserved address address address address address address reserved
byte n + 1
0
0 0 0 0 0 00
[1] All reserved bits must be set to logic 0.
9.1.4.2 SPI write data
The structure shown in Table 9 must be used to write data using SPI. It is possible to write
up to n-data bytes. The first byte sent defines both the mode and the address.
Table 9.
MOSI
MISO
SPI write data
Byte 0
address
XX
Byte 1
data 0
XX
Byte 2
data 1
XX
The address byte must meet the following criteria:
... Byte n
... data n 1
... XX
Byte n + 1
data n
XX
• the MSB of the first byte sets the mode. To write data to the MFRC530, the MSB is set
to logic 0
• bits [6:1] define the address
• the LSB should be set to logic 0.
SPI write mode writes all data to the address defined in byte 0 enabling effective write
cycles to the FIFO buffer.
Table 10. SPI write address
Address line Bit 7 Bit 6
(MOSI)
(MSB)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)[1]
byte 0
0 address address address address address address reserved
byte 1 to byte data data data data data data data data
n+1
[1] All reserved bits must be set to logic 0.
Remark: The data bus pins D7 to D0 must be disconnected.
Refer to Section 13.4.4 on page 95 for the timing specification.
MFRC530
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.4 — 12 February 2014
057434
© NXP B.V. 2014. All rights reserved.
11 of 115
11 Page | ||
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