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TC58TEG5DCJTAx0 PDF 데이터시트 ( Data , Function )

부품번호 TC58TEG5DCJTAx0 기능
기능 NAND memory Toggle DDR1.0
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TC58TEG5DCJTAx0 데이터시트, 핀배열, 회로
TOSHIBA CONFIDENTIAL TC58TEG5DCJTAx0
TOSHIBA
NAND memory
Toggle DDR1.0
Technical Data Sheet
Rev. 0.2
2012 – 03 – 01
TOSHIBA
Semiconductor & Storage Products
Memory Division
0 TENTATIVE 2012-03-01C




TC58TEG5DCJTAx0 pdf, 반도체, 판매, 대치품
TOSHIBA CONFIDENTIAL TC58TEG5DCJTAx0
LIST of FIGURES
Figure 1. Block Diagram .......................................................................................................................................... 11
Figure 2. Overshoot/Undershoot Diagram .............................................................................................................. 14
Figure 3. tRISE and tFALL Definition for Output Slew Rate ...................................................................................... 20
Figure 4. Write Protect timing requirements of the Program operation ............................................................... 21
Figure 5. Write Protect timing requirements of the Erase operation .................................................................... 21
Figure 6. Target Organization ................................................................................................................................. 22
Figure 7. Row Address Layout ................................................................................................................................. 23
Figure 8. Position of Plane Address ......................................................................................................................... 23
Figure 9. Area marked in first or last page of block indicating defect ................................................................... 25
Figure 10. Flow chart to create initial invalid block table ..................................................................................... 26
Figure 11. Initialization Timing............................................................................................................................... 28
Figure 12. Command Latch Cycle Timing............................................................................................................... 30
Figure 13. Address Latch Cycle Timing .................................................................................................................. 30
Figure 14. Basic Data Input Timing........................................................................................................................ 31
Figure 15. Basic Data Output Timing ..................................................................................................................... 32
Figure 16. Read ID Operation Timing..................................................................................................................... 33
Figure 17. Status Read Cycle Timing ...................................................................................................................... 34
Figure 18. Set Feature Timing................................................................................................................................. 35
Figure 19. Get Feature Timing ................................................................................................................................ 35
Figure 20. Page Read Operation Timing ................................................................................................................. 36
Figure 21. Read Hold Operation with CE high..................................................................................................... 36
Figure 22. Page Program Operation Timing ........................................................................................................... 37
Figure 23. Command Latch Cycle Timing............................................................................................................... 38
Figure 24. Address Latch Cycle Timing .................................................................................................................. 38
Figure 25. Basic Data Input Timing........................................................................................................................ 39
Figure 26. Basic Data Output Timing ..................................................................................................................... 39
Figure 27. Read ID Operation Timing..................................................................................................................... 40
Figure 28. Status Read Cycle Timing ...................................................................................................................... 40
Figure 29. Set Feature Timing................................................................................................................................. 41
Figure 30. Get Feature Timing ................................................................................................................................ 41
Figure 31. Page Read Operation Timing ................................................................................................................. 42
Figure 32. Page Program Operation Timing ........................................................................................................... 43
Figure 33. Page Read Timing................................................................................................................................... 50
Figure 34. Page Read with Random Data Output Timing ..................................................................................... 50
Figure 35. Data Out After Status Read Timing ...................................................................................................... 51
Figure 36. Sequential Cache Read Timing.............................................................................................................. 51
Figure 37. Random Cache Read Timing .................................................................................................................. 52
Figure 38. Page Program Timing............................................................................................................................. 52
Figure 39. Program operation with Random Data Input Timing .......................................................................... 52
Figure 40. Cache Program Timing........................................................................................................................... 53
Figure 41. Block Erase Timing ................................................................................................................................ 53
Figure 42. Copy-Back Program Timing ................................................................................................................... 54
Figure 43. Copy-Back Program with Random Data Input Timing ........................................................................ 54
Figure 44. Set Feature Timing................................................................................................................................. 55
Figure 45. Get Feature Timing ................................................................................................................................ 56
Figure 46. Read ID Timing ...................................................................................................................................... 57
Figure 47. Read Status Timing ................................................................................................................................ 59
Figure 48. Reset timing............................................................................................................................................ 60
Figure 49. Reset timing during Program operation................................................................................................ 60
Figure 50. Reset timing during Erase operation..................................................................................................... 60
Figure 51. Reset timing during Read operation...................................................................................................... 60
Figure 52. Status Read after Reset operation ......................................................................................................... 61
Figure 53. Successive Reset operation..................................................................................................................... 61
Figure 54. Single LUN Reset Timing ...................................................................................................................... 62
Figure 55. Example Timing with Page Copy (2) ..................................................................................................... 63
Figure 56. Device Identification Table Read Timing .............................................................................................. 64
Figure 57. Read Status Timing ................................................................................................................................ 70
Figure 58. Read LUN#0 Status Timing................................................................................................................... 71
3 TENTATIVE 2012-03-01C

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TC58TEG5DCJTAx0 전자부품, 판매, 대치품
TOSHIBA CONFIDENTIAL TC58TEG5DCJTAx0
LUN (Logical Unit Number)
The minimum unit that can independently execute commands and report status. There are one or more LUNs per
CE .
Target
An independent NAND Flash component with its own CE signal.
SR[x] (Status Read)
SR refers to the status register contained within a particular LUN. SR[x] refers to bit x in the status register for
the associated LUN. Refer to section 5.13 for the definition of bit meanings within the status register.
6 TENTATIVE 2012-03-01C

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TC58TEG5DCJTAx0

NAND memory Toggle DDR1.0

Toshiba
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