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부품번호 P6103AS8 기능
기능 5V/12V Synchronous-Rectified Buck Controller
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P6103AS8 데이터시트, 핀배열, 회로
uP6103
5V/12V Synchronous-Rectified
Buck Controller with Reference Input
General Description
Features
The uP6103 is a compact synchronous-rectified buck
controller specifically designed to operate from 5V or 12V
supply voltage and to deliver high quality output voltage as
low as 0.4V. These SOP-8 and PSOP-8 devices operate at
fixed 200/300 kHz frequency and provide an optimal level
of integration to reduce size and cost of the power supply.
The uP6103 supports both tracking mode and stand-alone
mode operation. The output voltage is tightly regulated to
the external reference voltage from 0.4V to 3.0V at tracking
mode or to internal 0.6V reference at stand-alone mode.
This controller integrates internal MOSFET drivers that
support 12V+12V bootstrapped voltage for high efficiency
power conversion. The bootstrap diode is built-in to simplify
the circuit design and minimize external part count.
Other features include internal softstart, undervoltage
protection, overcurrent protection and shutdown function.
With aforementioned functions, this part provides
customers a compact, high efficiency, well-protected and
cost-effective solutions. This part is available in SOP-8 and
PSOP-8 packages.
Ordering Information
Order Number Package Top Marking
Remark
uP6103S8 SOP-8L uP6103S8
200kHz
uP6103AS8 SOP-8L uP6103AS8
300kHz
uP6103ASU8 PSOP-8L uP6103ASU8
300kHz
Note: uPI products are compatible with the current IPC/
JEDEC J-STD-020 requirements. They are halogen-free,
RoHS compliant and 100% matte tin (Sn) plating that are
suitable for use in SnPb or Pb-free soldering processes.
† Operate from 5V or 12V Supply Voltage
† 3.3V to 12V VIN Input Range
† 0.6 VREF with 1.5% Accuracy
† Output Range from VREF to 80% of VIN
† Support Tracking Mode and Stand Alone Mode
Operation
† Simple Single-Loop Control Design
† Voltage-Mode PWM Control
† Fast Transient Response
† High-Bandwidth Error Amplifier
† 0% to 80% Duty Cycle
† Lossless, Programmable Overcurrent Protection
† Uses Lower MOSFET RDS(ON)
† 200/300 kHz Fixed Frequency Oscillator
† Internal Soft Start
† Integrated Bootstrap Diode
† RoHS Compliant and Halogen Free
Applications
† Power Supplies for Microprocessors or
Subsystem Power Supplies
† Cable Modems, Set Top Boxes, and xDSL
Modems
† Industrial Power Supplies; General Purpose
Supplies
† 5V or 12V Input DC-DC Regulators
† Low Voltage Distributed Power Supplies
Pin Configuration & Typical Application Circuit
BOOT
UGATE
GND
LGATE
18
27
36
45
SOP-8
PHASE
REFIN
FB
VCC
BOOT
UGATE
GND
LGATE
18
27
GND
36
45
PSOP-8
PHASE
REFIN
FB
VCC
Reference
Input
Disable
Enable
REFIN
7
VCC
5
BOOT
1
UGATE
2
8 PHASE
FB
6
Option
4 LGATE
3
GND
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP6103-DS-F0000
VIN
VOUT
1




P6103AS8 pdf, 반도체, 판매, 대치품
uP6103
The uP6103 is a compact synchronous-rectified buck
controller specifically designed to operate from 5V or 12V
supply voltage and to deliver high quality output voltage as
low as 0.4V. These SOP-8 and PSOP-8 devices operate at
fixed 200/300 kHz frequency and provide an optimal level
of integration to reduce size and cost of the power supply.
The uP6103 supports both tracking mode and stand-alone
mode operation. The output voltage is tightly regulated to
the external reference voltage from 0.4V to 3.0V at tracking
mode or to internal 0.6V reference at stand-alone mode.
Supply Voltage
The VCC pin receives a well-decoupled 4.5V to 13.2V
supply voltage to power the uP6103 control circuit, the
lower gate driver and the bootstrap circuit for the higher
gate driver. A minimum 0.1uF ceramic capacitor is
recommended to bypass the supply voltage. Place the
bypassing capacitor physically near the IC.
An internal linear regulator regulates supply voltage into a
4.5V voltage 4.5VDD for internal control logic circuit. No
external bypass capacitor is required for filtering the 4.5VDD
voltage.
The uP6103 integrates MOSFET gate drives that are
powered from the VCC pin and support 12V+12V driving
capability. A bootstrap diode is embedded to facilitates PCB
design and reduce the total BOM cost. No external
Schottky diode is required. Converters that consist of
uP6103 feature high efficiency without special consideration
on the selection of MOSFETs.
Note: The embedded bootstrap diode is not a Schottky
diode having a 0.7V forward voltage. External
Schottky diode is highly recommended if the VCC
voltage is expected to be lower than 5.0V. Otherwise
the bootstrap diode may be too low for the device to
work normally.
Power On Reset and Chip Enable
A power on reset (POR) circuitry continuously monitors
the supply voltage at VCC pin. Once the rising POR
threshold is exceeded, the uP6103 sets itself to active
state and is ready to accept chip enable command. The
rising POR threshold is typically 4.2V at VCC rising.
The REFIN is a multifunctional pin: external reference input
and chip enable as shown in Figure 1. To Select Internal
0.6V Reference Voltage, just let the REFIN open. A 100uA
current source tries to pull high the REFIN voltage after
POR that is monitored by the Enable Comparator monitors
for chip enable. A signal level transistor is adequate to pull
this pin down to ground and shut down the uP6103. As Q1
is turned off, the REFIN voltage is pulled high to 3.3VDD by
Functional Description
the 100uA current source. As the REFIN voltage acrosses
0.3V threshold level, the Enable Comparator initiates the
operation of the uP6103. The REFIN voltage is compared
with 3.0V voltage to select the reference voltage with 1ms
time delay after chip enabling. The internal 0.6V reference
voltage is selected as the REFIN pulled high to internal
3.3VDD. The softstart cycle is initiated after reference
selection is completed.
To Select External Reference Voltage, connect REFIN
to a voltage source range from 0.4V to 3V. As Q1 is turn
off, the REFIN voltage is aligned to the external reference
input. As the REFIN voltage acrosses 0.3V threshold level,
the Enable Comparator initiates the operation of the
uP6103. The REFIN voltage is compared with 3.0V voltage
to select the reference voltage with 1ms time delay after
chip enabling. The external reference input is selected as
the REFIN voltage is lower than 3.0V. The 100uA current
source is turn off if the external reference input is select to
eliminate the load effect on the reference input. The softstart
cycle is initiated after reference selection is completed.
Note that the 100uA current source will induces load
effect on the external reference input and causes the
REFIN voltage slightly higher than the external
reference input during the reference selection. Make
sure that the external reference input is strong enough
so that REFIN voltage will not be higher than 3.0V.
Reference
Input
Disable
Enable
Reference
Voltage Reference
Selection
4.5VDD
uP6103
100uA
VREF
(0.6V)
REFIN
7
3.0V
Q1 1ms
Chip Delay
0.3V
Enable
Figure 1. Chip Enable and Reference Selection Function
SoftStart
A built-in Soft Start is used to prevent surge current from
power supply input during turn on (referring to the Functional
Block Diagram). The error amplifier is a three-input device.
Reference voltage VREF or the internal soft start voltage SS
whichever is smaller dominates the behavior of the non-
inverting input of the error amplifier. SS internally ramps up
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP6103-DS-F0000
4

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P6103AS8 전자부품, 판매, 대치품
uP6103
Electrical Characteristics
Parameter
Symbol
Test Conditions
Min Typ Max Units
Oscillator
Free Running Frequency
uP6103
fOSC uP6103A
170 200 230 kHz
255 300 345 kHz
Ramp Amplitude
Error Amplifier
VOSC VCC = 12V
-- 1.0 -- VP-P
Open Loop DC Gain
AO Guaranteed by Design
55 70 -- dB
Gain-Bandwidth Product
GBW Guaranteed by Design
-- 10 -- MHz
Slew Rate
SR Guaranteed by Design
3 6 -- V/us
Transconductance
Guaranteed by Design
-- -- 0.7 mS
PWM Controller Gate Drivers
Upper Gate Sourcing Current
Upper Gate Sinking Current
Upper Gate RDS(ON) Sinking
Lower Gate Sourcing Current
Lower Gate Sinking Current
Lower Gate RDS(ON) Sinking
PHASE Falling to LGATE
Rising Delay
IUG_SRC
IUG_SNK
RUG_SNK
ILG_SRC
ILG_SNK
RLG_SNK
VBOOT - VPHASE = 12V, VBOOT - VUGATE = 6V
VBOOT - VPHASE = 12V, VUGATE - VPHASE= 6V
VUGATE - VPHASE = 0.1V
VCC - VLGATE = 6V
VLGATE = 6V
VLGATE = 0.1V
VCC = 12V; VPHASE < 1.2V to VLGATE > 1.2V
-- -1 --
-- 1.5 --
-- 2 4
-- -1 --
-- 2 --
-- 2 4
A
A
A
A
-- 30 90 ns
LGATE Falling to UGATE
Rising Delay
VCC = 12V; VLGATE < 1.2V to (VUGATE - VPHASE ) >
1.2V
--
30 90 ns
Reference Voltage
Nominal Feedback Voltage
Output Voltage Accuracy
VFB Stand Alone Mode
| VFB - VREFIN |, VREFIN = 0.4V ~ 1.0V, Tracking
Mode
| VFB - VREFIN | / VREFIN, VREFIN = 1.0V ~ 3.0V,
Tracking Mode
0.591 0.6 0.609 V
-- -- 15 mV
-- -- 1.5 %
REFIN Enable Threshold
Protection
VREFIN
-- 0.3 0.35 V
Under Voltage Protection
VFB_UVP
0.3 0.4 0.5 V
Over Current Threshold
VPHASE RLGATE Open
-- -375 -- mV
Soft-Start Interval
TSS Stand Alone Mode
2.4 3.6 4.8 ms
Note 1. Stresses listed as the above Absolute Maximum Ratingsmay cause permanent damage to the device.
These are for stress ratings. Functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 4. The device is not guaranteed to function outside its operating conditions.
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP6103-DS-F0000
7

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P6103AS8

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