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부품번호 ARM7TDMI
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ARM7TDMI 데이터시트, 핀배열, 회로
ARM7TDMI
Revision: r4p1
Technical Reference Manual
Copyright © 2001, 2004 ARM Limited. All rights reserved.
ARM DDI 0210C




ARM7TDMI pdf, 반도체, 판매, 대치품
Contents
Chapter 3
Chapter 4
Chapter 5
Chapter 6
iv
Memory Interface
3.1 About the memory interface ....................................................................... 3-2
3.2 Bus interface signals .................................................................................. 3-3
3.3 Bus cycle types .......................................................................................... 3-4
3.4 Addressing signals ................................................................................... 3-11
3.5 Address timing .......................................................................................... 3-14
3.6 Data timed signals .................................................................................... 3-17
3.7 Stretching access times ............................................................................ 3-29
3.8 Privileged mode access ............................................................................ 3-31
3.9 Reset sequence after power up ................................................................ 3-32
Coprocessor Interface
4.1 About coprocessors .................................................................................... 4-2
4.2 Coprocessor interface signals .................................................................... 4-4
4.3 Pipeline following signals ............................................................................ 4-5
4.4 Coprocessor interface handshaking ........................................................... 4-6
4.5 Connecting coprocessors ......................................................................... 4-12
4.6 If you are not using an external coprocessor ............................................ 4-15
4.7 Undefined instructions .............................................................................. 4-16
4.8 Privileged instructions ............................................................................... 4-17
Debug Interface
5.1 About the debug interface .......................................................................... 5-2
5.2 Debug systems ........................................................................................... 5-4
5.3 Debug interface signals .............................................................................. 5-7
5.4 ARM7TDMI core clock domains ............................................................... 5-11
5.5 Determining the core and system state .................................................... 5-13
5.6 About EmbeddedICE-RT logic ................................................................. 5-14
5.7 Disabling EmbeddedICE-RT .................................................................... 5-16
5.8 Debug Communications Channel ............................................................. 5-17
5.9 Monitor mode ............................................................................................ 5-21
Instruction Cycle Timings
6.1 About the instruction cycle timing tables .................................................... 6-3
6.2 Branch and branch with link ....................................................................... 6-4
6.3 Thumb branch with link ............................................................................... 6-5
6.4 Branch and Exchange ................................................................................ 6-6
6.5 Data operations .......................................................................................... 6-7
6.6 Multiply and multiply accumulate ................................................................ 6-9
6.7 Load register ............................................................................................. 6-12
6.8 Store register ............................................................................................ 6-14
6.9 Load multiple registers ............................................................................. 6-15
6.10 Store multiple registers ............................................................................. 6-17
6.11 Data swap ................................................................................................. 6-18
6.12 Software interrupt and exception entry ..................................................... 6-19
6.13 Coprocessor data operation ..................................................................... 6-20
Copyright © 2001, 2004 ARM Limited. All rights reserved.
ARM DDI 0210C

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ARM7TDMI 전자부품, 판매, 대치품
List of Tables
ARM7TDMI Technical Reference Manual
Table 1-1
Table 1-2
Table 1-3
Table 1-4
Table 1-5
Table 1-6
Table 1-7
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 3-1
Table 3-2
Table 3-3
Table 3-4
Table 3-5
Table 3-6
Table 3-7
Table 3-8
Table 4-1
Table 4-2
ARM DDI 0210C
Change history .............................................................................................................. ii
Key to tables ........................................................................................................... 1-11
ARM instruction summary ....................................................................................... 1-13
Addressing modes .................................................................................................. 1-16
Operand 2 ............................................................................................................... 1-18
Fields ....................................................................................................................... 1-19
Condition fields ........................................................................................................ 1-19
Thumb instruction set summary .............................................................................. 1-22
Register mode identifiers .......................................................................................... 2-7
PSR mode bit values ............................................................................................... 2-15
Exception entry and exit .......................................................................................... 2-16
Exception vectors .................................................................................................... 2-21
Exception priority order ........................................................................................... 2-22
Bus cycle types ......................................................................................................... 3-5
Burst types ................................................................................................................ 3-7
Significant address bits ........................................................................................... 3-12
nOPC ...................................................................................................................... 3-12
nTRANS encoding .................................................................................................. 3-13
Tristate control of processor outputs ....................................................................... 3-21
Read accesses ........................................................................................................ 3-27
Use of nM[4:0] to indicate current processor mode ................................................ 3-31
Coprocessor availability ............................................................................................ 4-3
Handshaking signals ................................................................................................. 4-6
Copyright © 2001, 2004 ARM Limited. All rights reserved.
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