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기능 Integrator Series FPGAs
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A3265DX 데이터시트, 핀배열, 회로
Integrator Series FPGAs:
1200XL and 3200DX Families
Discontinued – v3.0
Features
High Capacity
• 2,500 to 30,000 Logic Gates
• Up to 3Kbits Configurable Dual-Port SRAM
• Fast Wide-Decode Circuitry
• Up to 250 User-Programmable I/O Pins
High Performance
• 225 MHz Performance
• 5 ns Dual-Port SRAM Access
• 100 MHz FIFOs
• 7.5 ns 35-Bit Address Decode
Ease-of-Integration
• Synthesis-Friendly Architecture Supports ASIC Design
Methodologies.
• 95–100% Device Utilization using Automatic
Place-and-Route Tools.
• Deterministic, User-Controllable Timing Via Timing
Driven Software Tools with Up To 100% Pin Fixing.
• IEEE Standard 1149.1 (JTAG) Boundary Scan Testing.
General Description
Actel’s Integrator Series FPGAs are the first programmable
logic devices optimized for high-speed system logic
integration. Based on Actel’s proprietary antifuse
technology and 0.6-micron double metal CMOS process,
Integrator Series devices offer a fine-grained, register-rich
architecture with embedded dual-port SRAM and
wide-decode circuitry.
Integrator Series’ 3200DX and 1200XL families were
designed to integrate system logic which is typically
implemented in multiple CPLDs, PALs, and FPGAs. These
devices provide the features and performance required for
today’s complex, high-speed digital logic systems. The
3200DX family offers fast dual-port SRAM for implementing
FIFOs, LIFOs, and temporary data storage. The large
number of storage elements can efficiently address
applications requiring wide datapath manipulation and
transformation functions such as telecommunications,
networking, and DSP.
Integrator Series Product Profile Family
Device
Capacity
Logic Gates1
SRAM Bits
Logic Modules
Sequential
Combinatorial
Decode
SRAM Modules
(64x4 or 32x8)
Dedicated Flip-Flops
Clocks
User I/O (Maximum)
JTAG
A1225XL
2,500
N/A
231
220
N/A
N/A
231
2
83
No
1200XL
A1240XL
4,000
N/A
348
336
N/A
N/A
348
2
104
No
A1280XL
8,000
N/A
624
608
N/A
N/A
624
2
140
No
A3265DX
6,500
N/A
510
475
20
N/A
510
2
126
No
Packages
PL84
PQ100
VQ100
PG100
PL84 PQ100
PQ144
TQ176
PG132
PL84
PQ160 PQ208
TQ176
PG176 CQ172
Note: Logic gate capacity does not include SRAM bits as logic.
PL84
PQ100
PQ160
TQ176
A32100DX
3200DX
A32140DX
A32200DX
A32300DX
10,000
2,048
700
662
20
8
700
6
152
Yes
PL84
PQ160
PQ208
TQ176
CQ84
14,000
N/A
954
912
24
N/A
954
2
176
Yes
PL84
PQ160
PQ208
TQ176
CQ256
20,000
2,560
1,230
1,184
24
10
1,230
6
202
Yes
PQ208
RQ208
RQ240
CQ208
CQ256
30,000
3,072
1,888
1,833
28
12
1,888
6
250
Yes
RQ208
RQ240
CQ256
February 2001
© 2001 Actel Corporation
1




A3265DX pdf, 반도체, 판매, 대치품
Integrator Series FPGAs: 1200XL and 3200DX Families
Product Plan (Continued)
Speed Grade*
Application
–F Std –1 –2 –3
C I MB
176-Pin Thin Plastic Quad Flat Pack (TQFP)
✔✔✔✔✔
✔✔ — —
A32100DXV Device
84-Pin Plastic Leaded Chip Carrier (PLCC)
176-Pin Thin Plastic Quad Flat Pack (TQFP)
———
———
———
———
A32140DX Device
84-Pin Plastic Leaded Chip Carrier (PLCC)
160-Pin Plastic Quad Flat Pack (PQFP)
176-Pin Thin Plastic Quad Flat Pack (TQFP)
208-Pin Plastic Quad Flat Pack (PQFP)
256-Pin Ceramic Quad Flat Pack (CQFP)
✔✔✔✔
✔✔✔✔
✔✔✔✔
✔✔✔✔
✔✔— —
✔✔ — —
✔✔ — —
✔✔ — —
✔✔ — —
✔✔
A32140DXV Device
84-Pin Plastic Leaded Chip Carrier (PLCC)
176-Pin Thin Plastic Quad Flat Pack (TQFP)
———
———
———
———
A32200DX Device
208-Pin Plastic Quad Flat Pack (PQFP)
208-Pin Plastic Power Quad Flat Pack (RQFP)
240-Pin Plastic Power Quad Flat Pack (RQFP)
208-Pin Ceramic Quad Flat Pack (CQFP)
256-Pin Ceramic Quad Flat Pack (CQFP)
✔✔✔✔✔
✔✔✔✔✔
✔✔✔✔✔
✔✔— —
✔✔— —
✔✔ — —
✔✔ — —
✔✔ — —
✔✔
✔✔
A32200DXV Device
208-Pin Plastic Quad Flat Pack (PQFP)
240-Pin Plastic Power Quad Flat Pack (RQFP)
———
———
———
———
A32300DX Device
208-Pin Plastic Power Quad Flat Pack (RQFP)
240-Pin Plastic Power Quad Flat Pack (RQFP)
256-Pin Ceramic Quad Flat Pack (CQFP)
✔✔✔✔✔
✔✔✔✔✔
✔✔— —
✔✔ — —
✔✔ — —
✔✔
A32300DXV Device
208-Pin Plastic Power Quad Flat Pack (RQFP)
———
———
240-Pin Plastic Power Quad Flat Pack (RQFP)
———
———
Contact your Actel sales representative for product availability.
Applications: C = Commercial Availability:
= Available *Speed Grade:
–1 = Approx. 15% faster than Standard
I = Industrial
P = Planned
–2 = Approx. 25% faster than Standard
M = Military
— = Not Planned
–3 = Approx. 35% faster than Standard
–F = Approx. 40% slower than Standard
Only Std, –1, –2 Speed Grade
Only Std, –1 Speed Grade
4 Discontinued – v3.0

4페이지










A3265DX 전자부품, 판매, 대치품
Integrator Series FPGAs: 1200XL and 3200DX Families
3200DX devices contain a third type of logic module,
D-modules, which are arranged around the periphery of the
device. D-modules contain wide-decode circuitry which
provides a fast, wide-input AND function similar to that
found in product term architectures (Figure 3). The
D-module allows 3200DX devices to perform wide-decode
functions at speeds comparable CPLDs and PAL devices.
The output of the D-module has a programmable inverter
for active HIGH or LOW assertion. The D-module output is
hard-wired to an output pin or can be fed back into the
array to be incorporated into other logic.
Dual-Port SRAM Modules
Several 3200DX devices contain dual-port SRAM modules
that have been optimized for synchronous or asynchronous
applications. The SRAM modules are arranged in 256-bit
blocks which can be configured as 32x8 or 64x4 (refer to
“Integrator Series Product Profile Family” on page 1 for the
number of SRAM blocks within a particular device). SRAM
modules can be cascaded together to form memory spaces
of user-definable width and depth. A block diagram of the
3200DX dual-port SRAM block is shown in Figure 4.
7 Inputs
Programmable
Inverter
Hard-Wire to I/O
Feedback to Array
Figure 3 • D-Module Implementation
WD[7:0]
Latches
[7:0]
WRAD[5:0]
[5:0]
Latches
Write
Port
Logic
SRAM Module
32 x 8 or 64 x 4
(256 Bits)
Read
Port
Logic
MODE
BLKEN
WEN
WCLK
Write
Logic
RD[7:0]
Routing Tracks
[5:0] RDAD[5:0]
Latches
Read
Logic
REN
RCLK
Figure 4 • 3200DX Dual-Port SRAM Block
The 3200DX SRAM modules are true dual-port structures
containing independent READ and WRITE ports. Each
SRAM module contains six bits of read and write addressing
(RDAD[5:0] and WRAD[5:0], respectively) for 64x4 bit
blocks. When configured in byte mode, the highest order
address bits (RDAD5 and WRAD5) are not used. The read
and write ports of the SRAM block contain independent
clocks (RCLK and WCLK) with programmable polarities
offering active HIGH or LOW implementation. The SRAM
block contains eight data inputs (WD[7:0]) and eight
outputs (RD[7:0]) which are connected to segmented
vertical routing tracks.
The 3200DX dual-port SRAM blocks provide an optimal
solution for high-speed buffered applications requiring fast
FIFO and LIFO queues. Actel’s ACTgen Macro Builder
provides the capability to quickly design memory functions,
Discontinued – v3.0
7

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A3265DX

Integrator Series FPGAs

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