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부품번호 | HCTS75D 기능 |
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기능 | Radiation Hardened Dual 2-Bit Bistable Transparent Latch | ||
제조업체 | Intersil Corporation | ||
로고 | |||
HCTS75MS
September 1995
Radiation Hardened
Dual 2-Bit Bistable Transparent Latch
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm2/mg
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-Day
(Typ)
• Dose Rate Survivability: >1 x 1012 RAD (Si)/s
• Dose Rate Upset >1010 RAD (Si)/s 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current Levels Ii ≤ 5µA at VOL, VOH
Description
The Intersil HCTS75MS is a Radiation Hardened dual 2-bit
bistable transparent latch. Each of the two latches are controlled
by a separate enable input (E) which are active low. E low latches
the output state.
The HCTS75MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of radia-
tion hardened, high-speed, CMOS/SOS Logic Family.
The HCTS75MS is supplied in a 16 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
PART
NUMBER
HCTS75DMSR
HCTS75KMSR
HCTS75D/
Sample
HCTS75K/
Sample
HCTS75HMSR
TEMPERATURE SCREENING
RANGE
LEVEL
PACKAGE
-55oC to +125oC Intersil Class
S Equivalent
16 Lead SBDIP
-55oC to +125oC Intersil Class 16 Lead Ceramic
S Equivalent Flatpack
+25oC
Sample
16 Lead SBDIP
+25oC
+25oC
Sample
Die
16 Lead Ceramic
Flatpack
Die
Pinouts
16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
TOP VIEW
Q0 1 1
D0 1 2
D1 1 3
E2 4
VCC 5
D0 2 6
D1 2 7
Q1 2 8
16 1 Q0
15 1 Q1
14 1 Q1
13 1 E
12 GND
11 2 Q0
10 2 Q0
9 2 Q1
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
(FLATPACK) MIL-STD-1835 CDFP4-F16, LEAD FINISH C
TOP VIEW
Q0 1
D0 1
D1 1
E2
VCC
D0 2
D1 2
Q1 2
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
1 Q0
1 Q1
1 Q1
1E
GND
2 Q0
2 Q0
2 Q1
Functional Diagram
2(6)
D0
13(4)
E
LATCH 0
DQ
LE LE
16(10
1(11
14(8
3(7)
D1
5 VCC
12 GND
LE LE
DQ
LATCH 1
TRUTH TABLE
15(9
INPUTS
DE
LH
HH
XL
OUTPUTS
QQ
LH
HL
Q0 Q0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
470
Spec Number 518625
File Number 3189.1
Specifications HCTS75MS
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETERS
SYMBOL
(NOTE 1)
CONDITIONS
Supply Current
ICC VCC = 5.5V, VIN = VCC or GND
Output Current
(Sink)
IOL VCC = VIH = 4.5V, VOUT = 0.4V, VIL = 0V
Output Current
(Source)
IOH VCC = VIH = 4.5V, VOUT = VCC - 0.4V,
VIL = 0V
Output Voltage Low
VOL
VCC = 5.5V, VIH = 2.75V, VIL = 0.8V,
IOL = 50µA
VCC = 4.5V, VIH = 2.25V, VIL = 0.8V,
IOL = 50µA
Output Voltage High
VOH
VCC = 5.5V, VIH = 2.75V, VIL = 0.8V,
IOH = -50µA
VCC = 4.5V, VIH = 2.25V, VIL = 0.8V,
IOH = -50µA
Input Leakage
Current
IIN VCC = 5.5V, VIN = VCC or GND
Noise Immunity
Functional Test
FN VCC = 4.5V, VIH = 2.25V, VIL = 0.8V,
(Note 3)
Propagation Delay
D to Q
TPHL
TPLH
VCC = 4.5V, VIH = 3.0V, VIL = 0V
VCC = 4.5V, VIH = 3.0V, VIL = 0V
Propagation Delay
D to Q
TPHL
TPLH
VCC = 4.5V, VIH = 3.0V, VIL = 0V
VCC = 4.5V, VIH = 3.0V, VIL = 0V
Propagation Delay
E to Q
TPHL
TPLH
VCC = 4.5V, VIH = 3.0V, VIL = 0V
VCC = 4.5V, VIH = 3.0V, VIL = 0V
Propagation Delay
E to Q
TPHL
TPLH
VCC = 4.5V, VIH = 3.0V, VIL = 0V
VCC = 4.5V, VIH = 3.0V, VIL = 0V
TEMPERATURE
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
+25oC
200K RAD
LIMITS
MIN MAX UNITS
- 0.4 mA
4.0 - mA
-4.0 - mA
- 0.1 V
- 0.1 V
VCC
-0.1
VCC
-0.1
-5
-
-
+5
V
V
µA
--
2 35 ns
2 24 ns
2 22 ns
2 29 ns
2 23 ns
2 25 ns
2 34 ns
2 29 ns
NOTES:
1. All voltages referenced to device GND.
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.
3. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.
TABLE 5. BURN-IN AND OPERATING LIFE DELTA PARAMETERS (+25oC)
PARAMETER
GROUP B
SUBGROUP
DELTA LIMIT
ICC 5 ±6µA
IOL/IOH
5 -15% of 0 Hour
Spec Number 518625
473
4페이지 HCTS75MS
Propagation Delay Timing Diagram and Load Circuit
VIH
VSS
VOH
VOL
VS INPUT
TPLH
TPHL
VS OUTPUT
DUT
50pF
TEST
500Ω
Transition Timing Diagram
VOH
VOL
TTLH
20%
80% 80%
OUTPUT
TTHL
20%
PARAMETER
VCC
VIH
VS
VIL
GND
VOLTAGE LEVELS
HCTS
4.50
3.00
1.30
0
0
UNITS
V
V
V
V
V
Pulse Width, Setup, Hold Timing Diagram and Load Circuit
D INPUT
VIH
VIL
VS
E INPUT
VIH
VIL
TH
TSU
TW
VS
TH = Hold Time
TSU = Setup Time
TW = Pulse Width
DUT
50pF
TEST
500Ω
PARAMETER
VCC
VIH
VS
VIL
GND
VOLTAGE LEVELS
HCTS
4.50
4.50
2.25
0
0
UNITS
V
V
V
V
V
Pulse Width, Setup, Hold Timing Diagram Negative Edge Trigger and Load Circuit
INPUT
VIH
VIL
VS
INPUT CP
VIH
VIL
TW
TSU
TH
TW
VS
TH = Hold Time
TSU = Setup Time
TW = Pulse Width
DUT
50pF
TEST
500Ω
PARAMETER
VCC
VIH
VS
VIL
GND
VOLTAGE LEVELS
HCTS
4.50
4.50
2.25
0
0
UNITS
V
V
V
V
V
Spec Number 518625
476
7페이지 | |||
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부품번호 | 상세설명 및 기능 | 제조사 |
HCTS75D | Radiation Hardened Dual 2-Bit Bistable Transparent Latch | Intersil Corporation |
HCTS75DMSR | Radiation Hardened Dual 2-Bit Bistable Transparent Latch | Intersil Corporation |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |