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PDF AKD4628A Data sheet ( Hoja de datos )
| Número de pieza | AKD4628A | |
| Descripción | High Performance Multi-channel Audio CODEC | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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ASAHI KASEI
[AK4628A]
AK4628A
High Performance Multi-channel Audio CODEC
GENERAL DESCRIPTION
The AK4628A is a single chip CODEC that includes two channels of ADC and eight channels of DAC. The
ADC outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual Bit
architecture with wide dynamic range. The DAC introduces the newly developed Advanced Multi-Bit
architecture, and achieves wider dynamic range and lower outband noise. An auxiliary digital audio input
interface maybe used instead of the ADC for passing audio data to the primary audio output port. Control
may be set directly by pins or programmed through a separate serial interface.
The AK4628A has a dynamic range of 102dB for ADC, 106dB for DAC and is well suited for digital
surround for home theater and car audio. An AC-3 system can be built with a IEC60958(SPDIF) receiver
such as the AK4112B. The AK4628A is available in a small 44pin LQFP package which will reduce
system space.
*AC-3 is a trademark of Dolby Laboratories.
FEATURES
2ch 24bit ADC
- 64x Oversampling
- Sampling Rate up to 96kHz
- Linear Phase Digital Anti-Alias Filter
- Single-Ended Input
- S/(N+D): 92dB
- Dynamic Range, S/N: 102dB
- Digital HPF for offset cancellation
- I/F format: MSB justified, I2S or TDM
- Overflow flag
8ch 24bit DAC
- 128x Oversampling
- Sampling Rate up to 192kHz
- 24bit 8 times Digital Filter
- Single-Ended Outputs
- On-chip Switched-Capacitor Filter
- S/(N+D): 90dB
- Dynamic Range, S/N: 106dB
- I/F format: MSB justified, LSB justified(20bit,24bit), I2S or TDM
- Individual channel digital volume with 128 levels and 0.5dB step
- Soft mute
- De-emphasis for 32kHz, 44.1kHz and 48kHz
- Zero Detect Function
High Jitter Tolerance
TTL Level Digital I/F
3-wire Serial and I2C Bus µP I/F for mode setting
Master clock:256fs, 384fs or 512fs for fs=32kHz to 48kHz
128fs, 192fs or 256fs for fs=64kHz to 96kHz
128fs for fs=120kHz to 192kHz
Power Supply: 4.5 to 5.5V
Power Supply for output buffer: 2.7 to 5.5V
Small 44pin LQFP
AK4529 Pin Compatible
MS0385-E-00
-1-
2005/02
1 page  
ASAHI KASEI
No. Pin Name
1 SDOS
2 I2C
3 SMUTE
4 BICK
5 LRCK
6 SDTI1
7 SDTI2
8 SDTI3
9 SDTO
10 DAUX
11 DFS0
12 SDTI4
13 DZFE
14 TVDD
15 DVDD
16 DVSS
17 PDN
18 TST1
19 CAD1
20 CAD0
21 LOUT4
22 ROUT4
[AK4628A]
PIN/FUNCTION
I/O Function
I SDTO Source Select Pin
(Note 1)
“L”: Internal ADC output, “H”: DAUX input
SDOS pin should be set to “L” when TDM= “1”.
I Control Mode Select Pin
“L”: 3-wire Serial, “H”: I2C Bus
I Soft Mute Pin
(Note 1)
When this pin goes to “H”, soft mute cycle is initialized.
When returning to “L”, the output mute releases.
I Audio Serial Data Clock Pin
I Input Channel Clock Pin
I DAC1 Audio Serial Data Input Pin
I DAC2 Audio Serial Data Input Pin
I DAC3 Audio Serial Data Input Pin
O Audio Serial Data Output Pin
I AUX Audio Serial Data Input Pin
I Double Speed Sampling Mode Pin (Note 1)
“L”: Normal Speed, “H”: Double Speed
I DAC4 Audio Serial Data Input Pin
I Zero Input Detect Enable Pin
“L”: mode 7 (disable) at parallel mode,
zero detect mode is selectable by DZFM3-0 bits at serial mode
“H”: mode 0 (DZF1 is AND of all eight channels)
- Output Buffer Power Supply Pin, 2.7V∼5.5V
- Digital Power Supply Pin, 4.5V∼5.5V
- Digital Ground Pin, 0V
I Power-Down & Reset Pin
When “L”, the AK4628A is powered-down and the control registers are reset to default
state. If the state of P/S or CAD1-0 changes, then the AK4628A must be reset by PDN.
I Test Pin
This pin should be connected to DVSS.
I Chip Address 1 Pin
I Chip Address 0 Pin
O DAC4 Lch Analog Output Pin
O DAC4 Rch Analog Output Pin
MS0385-E-00
-5-
2005/02
5 Page 
ASAHI KASEI
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; CL=20pF)
Parameter
Symbol
min
Master Clock Timing
256fsn, 128fsd:
fCLK
8.192
Pulse Width Low
tCLKL
27
Pulse Width High
tCLKH
27
384fsn, 192fsd:
fCLK
12.288
Pulse Width Low
tCLKL
20
Pulse Width High
tCLKH
20
512fsn, 256fsd:
fCLK
16.384
Pulse Width Low
tCLKL
15
Pulse Width High
tCLKH
15
LRCK Timing
Normal mode (TDM0= “0”, TDM1= “0”)
Normal Speed Mode
fsn 32
Double Speed Mode
fsd 64
Quad Speed Mode
fsq 120
Duty Cycle
Duty
45
TDM256 mode (TDM0= “1”, TDM1= “0”)
LRCK frequency
fsn 32
“H” time
tLRH
1/256fs
“L” time
tLRL
1/256fs
TDM128 mode (TDM0= “1”, TDM1= “1”)
LRCK frequency
fsn 64
“H” time
tLRH
1/128fs
“L” time
tLRL
1/128fs
Audio Interface Timing
Normal mode (TDM0= “0”, TDM1= “0”)
BICK Period
tBCK
81
BICK Pulse Width Low
tBCKL
32
Pulse Width High
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
(Note 18)
(Note 18)
tBCKH
tLRB
tBLR
32
20
20
LRCK to SDTO(MSB)
BICK “↓” to SDTO
tLRS
tBSD
SDTI1-4,DAUX Hold Time
tSDH
20
SDTI1-4,DAUX Setup Time
tSDS
20
TDM256 mode (TDM0= “1”, TDM1= “0”)
BICK Period
tBCK
81
BICK Pulse Width Low
tBCKL
32
Pulse Width High
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
BICK “↓” to SDTO
(Note 18)
(Note 18)
tBCKH
tLRB
tBLR
tBSD
32
20
20
SDTI1 Hold Time
tSDH
10
SDTI1 Setup Time
tSDS
10
TDM128 mode (TDM0= “1”, TDM1= “1”)
BICK Period
tBCK
81
BICK Pulse Width Low
tBCKL
32
Pulse Width High
LRCK Edge to BICK “↑”
BICK “↑” to LRCK Edge
BICK “↓” to SDTO
(Note 18)
(Note 18)
tBCKH
tLRB
tBLR
tBSD
32
20
20
SDTI1-2 Hold Time
tSDH
10
SDTI1-2 Setup Time
tSDS
10
typ
Notes: 18. BICK rising edge must not occur at the same time as LRCK edge.
MS0385-E-00
- 11 -
[AK4628A]
max
12.288
18.432
24.576
Units
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
48 kHz
96 kHz
192 kHz
55 %
48 kHz
ns
ns
96 kHz
ns
ns
ns
ns
ns
ns
ns
ns
40 ns
40 ns
ns
ns
ns
ns
ns
ns
ns
ns
20 ns
ns
ns
ns
ns
ns
ns
ns
ns
20 ns
ns
ns
2005/02
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AKD4628A.PDF ] | |
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