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부품번호 | CH7308A-TF-TR 기능 |
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기능 | LVDS Transmitter | ||
제조업체 | Chrontel | ||
로고 | |||
Chrontel
CH7308
CH7308 SDVO1 LVDS Transmitter
Features
General Description
• Single/Dual LVDS Transmitter up to 140Mpixels/s
(CH7308A)
• Single/Dual LVDS Transmitter up to 165Mpixels/s
(CH7308B)
• Support resolutions up to 1600x1200 (1920x1200
with reduced blanking)
• LVDS low jitter PLL accepts spread spectrum input
• LVDS 18-bit and 24-bit outputs
• 2D dither engine
• Panel protection and power sequencing
• High-speed SDVO1 serial (1G~2Gbps) AC-coupled
differential RGB inputs
• Low voltage interface support to graphics device
• Programmable power management
• Fully programmable through serial port
• Configuration through OpCodes1
• Complete Windows driver support
• Boundary scan support
• Offered in a 64-pin LQFP package
1Intel Proprietary
The CH7308 is a display controller device, which accepts
digital graphics input signals, upscales, encodes, and transmits
data through an LVDS transmitter to a LCD panel. This
device accepts one channel of RGB data over three pairs of
serial data ports.
The LVDS Transmitter includes a low jitter PLL to generate a
high frequency serialized clock and all circuitry required to
upscale, encode, serialize and transmit data. The CH7308A
supports a maximum single channel pixel rate of 140MP/s
while the CH7308B supports a maximum pixel rate of
165MP/s. The minimum dual channel pixel rate is 100MP/s.
The LVDS transmitter includes a panel fitting up-scaler and a
programmable dither function to support 18-bit LCD panels.
Data is encoded into commonly used formats, including those
specified in the OpenLDI and SPWG specifications.
Serialized data is outputted on three to eight differential
channels.
RESET*
AS
SPC
SPD
SDVO_CLK(+/-)
SDVO_R(+/-)
SDVO_G(+/-)
SDVO_B(+/-)
Serial Port/
Power
Control
Clock Driver
Data Latch,
Serial To
Parallel
STALL(+/-) Generator/
Power Sequencing
SDVO
Character
Decoder
Up-Scaler
XTAL
SC_PROM
SD_PROM
SC_DDC
SD_DDC
SDVO_STALL(+/-)
ENAVDD
ENABKL
XI/FIN, XO
Dither
LVDS PLL
LVDS
Encoder
FIFO
LVDS
Serializer
LVDS
Driver
Figure 1: Functional Block Diagram
LDC[3:0],LDC*[3:0]
LL1C,LL1C*
LDC[7:4],LDC*[7:4]
LL2C,LL2C*
VSWING
201-0000-064 Rev. 2.3, 9/22/2008
1
CHRONTEL
1.2 Pin Description
Table 1: Pin Description
Pin #
4
Type
In
Symbol
RESET*
5 In AS
6 In/Out SPC
7 In/Out SPD
9 In/Out SD_PROM
10 In/Out SC_PROM
11 In/Out SD_DDC
12 In/Out SC_DDC
2 Out ENAVDD
1 Out ENABKL
63 In BSCAN
50 Out TEST
64 In Reserved
CH7308
Description
Reset* Input (Internal pull-up)
When this pin is low, the device is held in the power-on reset
condition. When this pin is high, reset is controlled through the
serial port interface.
Address Select (Internal pull-up)
This pin determines the serial port address of the device
(0,1,1,1,0,0,AS*,0).
Serial Port Clock Input
This pin functions as the clock input of the serial port interface
and operates with from 0 to 2.5V. This pin requires an external
4kΩ - 9kΩ pull up resistor to 2.5V
Serial Port Data Input/Output
This pin functions as the bi-directional data pin of the serial port
interface and operates with inputs from 0 to 2.5V. Outputs are
driven from 0 to 2.5V. This pin requires an external 4kΩ - 9kΩ
pull up resistor to 2.5V.
Routed Data Output to PROM
This pin functions as the bi-directional data pin of the serial port
interface for the external 5V serial EEPROM used for ADD2 card
designs. This pin requires an external 5.6K pull-up resistor to the
desired high state voltage. Leave open if unused.
Routed Clock Output to PROM
This pin functions as the clock bus of the serial port interface for
the external 5V serial EEPROM used for ADD2 card designs.
This pin requires an external 5.6K pull-up resistor to the desired
high state voltage. Leave open if unused.
Routed Serial Port Data Output to DDC
This pin functions as the bi-directional data pin of the serial port
to the DDC of the receiver. This pin requires an external 4–9kΩ
pull-up resistor to the desired high state voltage. Leave open if
unused.
Routed Serial Port Clock Output to DDC
This pin functions as the clock bus of the serial port to the DDC of
the receiver. This pin requires an external 4–9kΩ pull-up resistor
to the desired high state voltage. Leave open if unused.
Panel Power Enable
Enable LCD panel VDD (2.5V).
Backlight Enable
Enable backlight of LCD panel (2.5V).
BSCAN (internal pull low)
This pin should be left open.
TEST
Internal test pin to monitor the state of the ENEXBUF (External
Buffer Enable) signal. See TB49 for details. If the ENEXBUF
signal does not need to be monitored, this pin may be left open.
Reserved
This pin should be left open
4
201-0000-064
Rev. 2.3, 9/22/2008
4페이지 CHRONTEL
LDC[1](2)
LDC[1](3)
LDC[1](4)
LDC[1](5)
LDC[1](6)
LDC[1](7)
LDC[2](1)
LDC[2](2)
LDC[2](3)
LDC[2](4)
LDC[2](5)
LDC[2](6)
LDC[2](7)
LDC[3](1)
LDC[3](2)
LDC[3](3)
LDC[3](4)
LDC[3](5)
LDC[3](6)
LDC[3](7)
G2 / G2
G3 / G3
G4 / G4
G5 / G5
B0 / B0
B1 / B1
B2 / B2
B3 / B3
B4 / B4
B5 / B5
HSYNC / HSYNC
VSYNC / VSYNC
DE / DE
Table 4: Signal Mapping for Dual LVDS Channel
LDC[0](1)
LDC[0](2)
LDC[0](3)
LDC[0](4)
LDC[0](5)
LDC[0](6)
LDC[0](7)
LDC[1](1)
LDC[1](2)
LDC[1](3)
LDC[1](4)
LDC[1](5)
LDC[1](6)
LDC[1](7)
LDC[2](1)
LDC[2](2)
LDC[2](3)
LDC[2](4)
LDC[2](5)
LDC[2](6)
LDC[2](7)
LDC[3](1)
LDC[3](2)
LDC[3](3)
LDC[3](4)
LDC[3](5)
LDC[3](6)
LDC[3](7)
LDC[4](1)
LDC[4](2)
LDC[4](3)
LDC[4](4)
18-bit SPWG / 18-bit OpenLDI
Ro0 / Ro0
Ro1 / Ro1
Ro2 / Ro2
Ro3 / Ro3
Ro4 / Ro4
Ro5 / Ro5
Go0 / Go0
Go1 / Go1
Go2 / Go2
Go3 / Go3
Go4 / Go4
Go5 / Go5
Bo0 / Bo0
Bo1 / Bo1
Bo2 / Bo2
Bo3 / Bo3
Bo4 / Bo4
Bo5 / Bo5
HSYNC / HSYNC
VSYNC / VSYNC
DE / DE
Re0 / Re0
Re1 / Re1
Re2 / Re2
Re3 / Re3
201-0000-064 Rev. 2.3, 9/22/2008
CH7308
G2 / G4
G3 / G5
G4 / G6
G5 / G7
B0 / B2
B1 / B3
B2 / B4
B3 / B5
B4 / B6
B5 / B7
HSYNC / HSYNC
VSYNC / VSYNC
DE / DE
R6 / R0
R7 / R1
G6 / G0
G7 / G1
B6 / B0
B7 / B1
RES / RES
24-bit SPWG / 24-bit OpenLDI
Ro0 / Ro2
Ro1 / Ro3
Ro2 / Ro4
Ro3 / Ro5
Ro4 / Ro6
Ro5 / Ro7
Go0 / Ro2
Go1 / Ro3
Go2 / Go4
Go3 / Go5
Go4 / Go6
Go5 / Go7
Bo0 / Bo2
Bo1 / Bo3
Bo2 / Bo4
Bo3 / Bo5
Bo4 / Bo6
Bo5 / Bo7
HSYNC / HSYNC
VSYNC / VSYNC
DE / DE
Ro6 / Ro0
Ro7 / Ro1
Go6 / Ro0
Go7 / Go1
Bo6 / Bo0
Bo7 / Bo1
RES / RES
Re0 / Re2
Re1 / Re3
Re2 / Re4
Re3 / Re5
7
7페이지 | |||
구 성 | 총 22 페이지수 | ||
다운로드 | [ CH7308A-TF-TR.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
CH7308A-TF-TR | LVDS Transmitter | Chrontel |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |