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PDF AT25DQ321 Data sheet ( Hoja de datos )
| Número de pieza | AT25DQ321 | |
| Descripción | 2.7V Minimum SPI Serial Flash Memory | |
| Fabricantes | adesto | |
| Logotipo |  |
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AT25DQ321
32-Mbit, 2.7V Minimum SPI Serial Flash Memory
with Dual-I/O and Quad-I/O Support
Features
DATASHEET
(Not Recommended for New Designs)
Single 2.7V - 3.6V supply
Serial Peripheral Interface (SPI) compatible
Supports SPI Modes 0 and 3
Supports RapidS™ operation
Supports Dual- and Quad-Input Program
Supports Dual- and Quad-Output Read
Very high operating frequencies
100MHz for RapidS
85MHz for SPI
Clock-to-output (tV) of 5ns maximum
Flexible, optimized erase architecture for code + data storage applications
Uniform 4KB, 32KB, and 64KB Block Erase
Full Chip Erase
Individual sector protection with Global Protect/Unprotect feature
64 sectors of 64KB each
Hardware controlled locking of protected sectors via WP pin
Sector Lockdown
Make any combination of 64KB sectors permanently read-only
128-byte Programmable OTP Security Register
Flexible programming
Byte/Page Program (1 to 256 bytes)
Fast Program and Erase times
1.5ms typical Page Program (256 bytes) time
50ms typical 4KB Block Erase time
250ms typical 32KB Block Erase time
400ms typical 64KB Block Erase time
Program and Erase Suspend/Resume
Automatic checking and reporting of erase/program failures
Software controlled reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low power dissipation
7mA Active Read current (typical at 20MHz)
5µA Deep Power-Down current (typical)
Endurance: 100,000 program/erase cycles
Data retention: 20 years
Complies with full industrial temperature range
Industry standard green (Pb/Halide-free/RoHS compliant) package options
8-lead SOIC (208-mil wide)
8-pad Ultra-thin DFN (5 x 6 x 0.6mm)
16-lead SOIC (300-mil wide)
8718F–DFLASH–1/2014
1 page  
3. Block Diagram
Figure 3-1. Block Diagram
Control and
CS Protection Logic
SCK
SI (I/O0)
SO (I/O1)
Interface
Control
And
Logic
Y-Decoder
WP (I/O2)
HOLD (I/O3)
X-Decoder
Note: I/O3-0 pin naming convention is used for Dual-I/O and Quad-I/O commands.
I/O Buffers
and Latches
SRAM
Data Buffer
Y-Gating
Flash
Memory
Array
AT25DQ321 [DATASHEET]
8718F–DFLASH–1/2014
5
5 Page 
7.2 Dual-Output Read Array
The Dual-Output Read Array command is similar to the standard Read Array command and can be used to sequentially
read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has
been specified. Unlike the standard Read Array command however, the Dual-Output Read Array command allows two
bits of data to be clocked out of the device on every clock cycle rather than just one.
The Dual-Output Read Array command can be used at any clock frequency up to the maximum specified by fRDDO. To
perform the Dual-Output Read Array operation, the CS pin must first be asserted and the opcode of 3Bh must be clocked
into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the starting
address location of the first byte to read within the memory array. Following the three address bytes, a single dummy
byte must also be clocked into the device.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being
output on both the I/O1 and I/O0 pins. The data is always output with the MSB of a byte first, and the MSB is always
output on the I/O1 pin. During the first clock cycle, bit 7 of the first data byte will be output on the I/O1 pin while bit 6 of the
same data byte will be output on the I/O0 pin. During the next clock cycle, bits 5 and 4 of the first data byte will be output
on the I/O1 and I/O0 pins, respectively. The sequence continues with each byte of data being output after every four clock
cycles. When the last byte (3FFFFFh) of the memory array has been read, the device will continue reading back at the
beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the
beginning of the array.
Deasserting the CS pin will terminate the read operation and put the I/O1-0 pins into a high-impedance state. The CS pin
can be deasserted at any time and does not require that a full byte of data be read.
Figure 7-4. Dual-Output Read Array
CS
SCK
SI (I/O0)
SO (I/O1)
0 1 2 3 4 5 6 7 8 9 10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Opcode
Address Bits A23-A0
Don't Care
Output
Data Byte 1
Output
Data Byte 2
0 0 1 1 1 0 1 1AAAAAA
MSB
MSB
A A A X X X X X X X X D6 D4 D2 D0 D6 D4 D2 D0 D6 D4
MSB
High-impedance
D7 D5 D3 D1 D7 D5 D3 D1 D7 D5
MSB
MSB
AT25DQ321 [DATASHEET]
8718F–DFLASH–1/2014
11
11 Page | ||
| Páginas | Total 63 Páginas | |
| PDF Descargar | [ Datasheet AT25DQ321.PDF ] | |
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