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PDF MX25L3255D Data sheet ( Hoja de datos )
| Número de pieza | MX25L3255D | |
| Descripción | FLASH MEMORY | |
| Fabricantes | MACRONIX | |
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MX25L3255D
MX25L3255D
SECURITY SERIAL FLASH
SPECIFICATION
P/N: PM1431
REV. 0.03, MAR. 13, 2009
1
1 page  
PRELIMINARY
MX25L3255D
32M-BIT [x 1/x 2/x4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 33,554,432 x 1 bit structure or 16,772,216 x 2 bits (two I/O read mode) structure or 8,388,608 x 4 bits (four I/O
read mode) structure
• 1024 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• 64 Equal Blocks with 64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast read
- 1 I/O: 104MHz with 8 dummy cycles
- 4 I/O: 75MHz with 6 dummy cycles
- 2 I/O: 75MHz with 4 dummy cycles
- Fast access time: 104MHz serial clock (15pF + 1TTL Load) and 66MHz serial clock (30pF + 1TTL Load)
- Serial clock of four I/O read mode : 75MHz (15pF + TTL Load), which is equivalent to 300MHz
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Byte program time: 9us (typical)
- Continuously program mode (automatically increase address under word program mode)
- Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 25s(typ.) /chip
• Low Power Consumption
- Low active read current: 25mA(max.) at 104MHz, 20mA(max.) at 66MHz and 10mA(max.) at 33MHz
- Low active programming current: 20mA (max.)
- Low active erase current: 20mA (max.)
- Low standby current: 20uA (max.)
• Typical 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block Write Lock protection
- Additional 4K-bit secured OTP for unique identifier
- Permanent lock
- Read protection function
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
P/N: PM1431
REV. 0.03, MAR. 13, 2009
5
5 Page 
MX25L3255D
II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit one-time program area for setting device
unique serial number - Which may be set by factory or system customer. Please refer to table 2. 4K-bit secured
OTP definition.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going
through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to table of "security register definition" for security
register bit definition and table of "4K-bit secured OTP definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit se-
cured OTP mode, array access is not allowed.
Table 2. 4K-bit Secured OTP Definition
Address range
Size
xxx000~xxx00F
128-bit
xxx010~xxx1FF
3968-bit
Standard Factory Lock
ESN (electrical serial number)
N/A
Customer Lock
Determined by customer
P/N: PM1431
REV. 0.03, MAR. 13, 2009
11
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