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MX25L25635E 데이터시트 PDF




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기능 FLASH MEMORY
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MX25L25635E 데이터시트, 핀배열, 회로
MX25L25635E
MX25L25635E
HIGH PERFORMANCE
SERIAL FLASH SPECIFICATION
P/N: PM1532
REV. 0.01, NOV. 18, 2009
1




MX25L25635E pdf, 반도체, 판매, 대치품
MX25L25635E
Figure 20. Sector Erase (SE) Sequence (Command 20)................................................................................. 53
Figure 21. Block Erase (BE/EB32K) Sequence (Command D8/52)................................................................ 53
Figure 22. Chip Erase (CE) Sequence (Command 60 or C7).......................................................................... 53
Figure 23. Page Program (PP) Sequence (Command 02).............................................................................. 54
Figure 24. 4 x I/O Page Program (4PP) Sequence (Command 38)................................................................. 54
Figure 25. Continously Program (CP) Mode Sequence with Hardware Detection (Command AD).................. 55
Figure 26-1. Enter Parallel Mode (ENPLM) Sequence (Command 55)........................................................... 56
Figure 26-2. Exit Parallel Mode (EXPLM) Sequence (Command 45).............................................................. 56
Figure 26-3. Parallel Mode Read Identification (Parallel RDID) Sequence (Command 9F)............................ 56
Figure 26-4. Parallel Mode Read Electronic Manufacturer & Device ID (Parallel REMS) Sequence (Command
90)..................................................................................................................................................................... 57
Figure 26-5. Parallel Mode Release from Deep Power-down (RDP) and Read Electronic Signature (RES)
Sequence.......................................................................................................................................................... 57
Figure 26-6. Parallel Mode Read Array (Parallel READ) Sequence (Command 03)....................................... 58
Figure 26-7. Parallel Mode Page Program (Parallel PP) Sequence (Command 02)....................................... 58
Figure 27. Deep Power-down (DP) Sequence (Command B9)....................................................................... 59
Figure 28. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB).
.......................................................................................................................................................................... 59
Figure 29. Release from Deep Power-down (RDP) Sequence (Command AB).............................................. 59
Figure 30. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF)........ 60
Figure 31. Write Protection Selection (WPSEL) Sequence (Command 68).................................................... 60
Figure 32. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39)..................... 61
Figure 33. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C)................................. 61
Figure 34. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98)....................................... 61
Figure 35. Power-up Timing.............................................................................................................................. 62
Table 9. Power-Up Timing ................................................................................................................................ 62
INITIAL DELIVERY STATE............................................................................................................................... 62
RECOMMENDED OPERATING CONDITIONS......................................................................................................... 63
ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 64
DATA RETENTION..................................................................................................................................................... 64
LATCH-UP CHARACTERISTICS............................................................................................................................... 64
ORDERING INFORMATION....................................................................................................................................... 65
PART NAME DESCRIPTION..................................................................................................................................... 66
PACKAGE INFORMATION........................................................................................................................................ 67
REVISION HISTORY ................................................................................................................................................. 68
P/N: PM1532
REV. 0.01, NOV. 18, 2009
4

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MX25L25635E 전자부품, 판매, 대치품
MX25L25635E
GENERAL DESCRIPTION
MX25L25635E is 268,435,456 bits serial Flash memory, which is configured as 33,554,432 x 8 internally. When it
is in two or four I/O mode, the structure becomes 134,217,728 bits x 2 or 67,108,864 bits x 4. The MX25L25635E
features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus
signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device
is enabled by CS# input.
MX25L25635E, MXSMIOTM (Serial Multi I/O) flash memory, provides sequential read operation on whole chip and
multi-I/O features.
When it is in dual I/O mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and
data output. When it is in quad I/O mode, the SI pin, SO pin, WP# pin and HOLD# pin become SIO0 pin, SIO1 pin,
SIO2 pin and SIO3 pin for address/dummy bits input and data Input/Output. Parallel mode is also provided in this
device. It features 8 bit input/output for increasing throughputs. This feature is recommeded to be used for factory
production purpose.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for Continuously Program mode, and erase command is executes on sector (4K-byte),
block (32K-byte/64K-byte), or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 200uA DC cur-
rent.
The MX25L25635E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
Table 1. Additional Features
Part
Name
Additional
Protection and Security
Features
Flexible or
Individual block
4K-bit
(or sector)
secured OTP
protection
MX25L25635E
V
V
1 I/O Read
(80 MHz)
V
Read Performance
2 I/O Read
(70 MHz)
V
4 I/O Read
(70 MHz)
V
8 I/O Parallel
Mode
(6 MHz)
V
Additional
Features
Identifier
Part
Name
RES
REMS
REMS2
REMS4
RDID
(command: AB hex) (command: 90 hex) (command: EF hex) (command: DF hex) (command: 9F hex)
MX25L25635E
18 (hex)
C2 18 (hex)
C2 18 (hex)
C2 18 (hex)
C2 20 19 (hex)
P/N: PM1532
REV. 0.01, NOV. 18, 2009
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