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MX25L12836E 데이터시트 PDF




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기능 FLASH MEMORY
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MX25L12836E 데이터시트, 핀배열, 회로
MX25L6436E
MX25L12836E
MX25L6436E/MX25L12836E
HIGH PERFORMANCE
SERIAL FLASH SPECIFICATION
P/N: PM1514
REV. 1.0, JUL. 29, 2009
1




MX25L12836E pdf, 반도체, 판매, 대치품
MX25L6436E
MX25L12836E
Figure 23-3. Parallel Mode Read Identification (Parallel RDID) Sequence (Command 9F)............................ 52
Figure 23-4. Parallel Mode Read Electronic Manufacturer & Device ID (Parallel REMS) Sequence (Command
90)..................................................................................................................................................................... 53
Figure 23-5. Parallel Mode Release from Deep Power-down (RDP) and Read Electronic Signature (RES)
Sequence.......................................................................................................................................................... 53
Figure 23-6. Parallel Mode Read Array (Parallel READ) Sequence (Command 03)....................................... 54
Figure 23-7. Parallel Mode Page Program (Parallel PP) Sequence (Command 02)....................................... 54
Figure 24. Deep Power-down (DP) Sequence (Command B9)....................................................................... 54
Figure 25. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB).
.......................................................................................................................................................................... 55
Figure 26. Release from Deep Power-down (RDP) Sequence (Command AB).............................................. 55
Figure 27. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90 or EF or DF or CF)..
.......................................................................................................................................................................... 56
Figure 28. Write Protection Selection (WPSEL) Sequence (Command 68).................................................... 56
Figure 29. Single Block Lock/Unlock Protection (SBLK/SBULK) Sequence (Command 36/39)..................... 57
Figure 30. Read Block Protection Lock Status (RDBLOCK) Sequence (Command 3C)................................. 57
Figure 31. Gang Block Lock/Unlock (GBLK/GBULK) Sequence (Command 7E/98)....................................... 57
Figure 32. Power-up Timing.............................................................................................................................. 58
Table 9. Power-Up Timing ................................................................................................................................ 58
INITIAL DELIVERY STATE............................................................................................................................... 58
RECOMMENDED OPERATING CONDITIONS......................................................................................................... 59
ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 60
DATA RETENTION..................................................................................................................................................... 60
LATCH-UP CHARACTERISTICS............................................................................................................................... 60
ORDERING INFORMATION....................................................................................................................................... 61
PART NAME DESCRIPTION..................................................................................................................................... 62
PACKAGE INFORMATION........................................................................................................................................ 63
P/N: PM1514
REV. 1.0, JUL. 29, 2009
4

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MX25L12836E 전자부품, 판매, 대치품
MX25L6436E
MX25L12836E
GENERAL DESCRIPTION
MX25L6436E is 67,108,864 bits serial Flash memory, which is configured as 8,388,608 x 8 internally. When it
is in two or four I/O mode, the structure becomes 33,554,432 bits x 2 or 16,777,216 bits x 4. MX25L12836E is
134,217,728 bits serial Flash memory, which is configured as 16,777,216 x 8 internally. When it is in two or four I/O
mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x 4. The MX25L6436E/12836E features a se-
rial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are
a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled
by CS# input.
MX25L6436E/12836E provides high performance read mode, which may latch address and data on both rising and
falling edge of clock. By using this high performance read mode, the data throughput may be doubling. Moreover,
the performance may reach direct code execution, the RAM size of the system may be reduced and further saving
system cost.
MX25L6436E/12836E, MXSMIOTM (Serial Multi I/O) flash memory, provides sequential read operation on whole
chip and multi-I/O features.
When it is in dual I/O mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and
data output. When it is in quad I/O mode, the SI pin, SO pin, WP# pin and NC pin become SIO0 pin, SIO1 pin, SIO2
pin and SIO3 pin for address/dummy bits input and data Input/Output. Parallel mode is also provided in this device.
It features 8 bit input/output for increasing throughputs. This feature is recommended to be used for factory produc-
tion purpose.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-
fied page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for Continuously Program mode, and erase command is executes on sector (4K-byte),
block (32K-byte/64K-byte), or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 100uA DC cur-
rent.
The MX25L6436E/12836E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even
after 100,000 program and erase cycles.
Table 1. Additional Features
Additional
Features
Protection and Security
Part
Name
Flexible or
Individual block (or
sector) protection
4K-bit
secured OTP
MX25L6436E
MX25L12836E
V
V
Read Performance
1 I/O Read (104 Dual Read (70
MHz)
MHz)
VV
Quad Read
(70 MHz)
V
8 I/O Parallel
Mode
(6 MHz)
V
(Note 1)
Additional
Features
Identifier
Part
Name
MX25L6436E
MX25L12836E
RES
(command: AB hex)
16 (hex)
17 (hex)
REMS
(command: 90 hex)
C2 16 (hex)
C2 17 (hex)
REMS2
(command: EF hex)
C2 16 (hex)
C2 17 (hex)
REMS4
(command: DF hex)
C2 16 (hex)
C2 17 (hex)
RDID
(command: 9F hex)
C2 20 17 (hex)
C2 20 18 (hex)
Note 1: Only MX25L12836E provide parallel mode.
P/N: PM1514
REV. 1.0, JUL. 29, 2009
7

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MX25L12836E

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