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PDF MX25L6445E Data sheet ( Hoja de datos )
| Número de pieza | MX25L6445E | |
| Descripción | FLASH MEMORY | |
| Fabricantes | MACRONIX | |
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MX25L6445E
MX25L6445E
HIGH PERFORMANCE
SERIAL FLASH SPECIFICATION
P/N: PM1736
REV. 1.8, DEC. 26, 2011
1
1 page  
MX25L6445E
64M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O) FLASH MEMORY
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 64Mb: 67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two I/O mode) structure or 16,777,216 x 4 bits (four I/
O mode) structure
• 2048 Equal Sectors with 4K bytes each
- Any Sector can be erased individually
• 256 Equal Blocks with 32K bytes each
- Any Block can be erased individually
• 128 Equal Blocks with 64K bytes each
- Any Block can be erased individually
• Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
VCC = 2.7~3.6V
- Normal read
- 50MHz
- Fast read (Normal Serial Mode)
- 1 I/O: 104MHz with 8 dummy cycles
- 2 I/O: 70MHz with 4 dummy cycles
- 4 I/O: 70MHz with 6 dummy cycles
- Fast read (Double Transfer Rate Mode)
- 1 I/O: 50MHz with 6 dummy cycles
- 2 I/O: 50MHz with 6 dummy cycles
- 4 I/O: 50MHz with 8 dummy cycles
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Byte program time: 9us (typical)
- Continuously Program mode (automatically increase address under word program mode)
- Fast erase time: 60ms (typ.)/sector (4K-byte per sector) ; 0.7s(typ.) /block (64K-byte per block); 50s(typ.) /chip
• Low Power Consumption
- Low active read current: 19mA(max.) at 104MHz, 15mA(max.) at 66MHz and 10mA(max.) at 33MHz
- Low active programming current: 25mA (max.)
- Low active erase current: 25mA (max.)
- Low standby current: 50uA (max.)
- Deep power down current: 20uA (max.)
• Typical 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
P/N: PM1736
REV. 1.8, DEC. 26, 2011
5
5 Page 
MX25L6445E
Table 2. Protected Area Sizes
Status bit
BP3 BP2 BP1
000
000
001
001
010
010
011
011
100
100
101
101
110
110
111
111
Protection Area
BP0 64Mb
0 0 (none)
1 1 (2 blocks, block 126th-127th)
0 2 (4 blocks, block 124th-127th)
1 3 (8 blocks, block 120th-127th)
0 4 (16 blocks, block 112nd-127th)
1 5 (32 blocks, block 96th-127th)
0 6 (64 blocks, block 64th-127th)
1 7 (128 blocks, all)
0 8 (128 blocks, all)
1 9 (128 blocks, all)
0 10 (128 blocks, all)
1 11 (128 blocks, all)
0 12 (128 blocks, all)
1 13 (128 blocks, all)
0 14 (128 blocks, all)
1 15 (128 blocks, all)
Note: The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0.
II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit One-Time Program area for setting de-
vice unique serial number - Which may be set by factory or system maker. Please refer to Table 3. 4K-bit Se-
cured OTP Definition.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command), and going
through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)
command to set customer lock-down bit1 as "1". Please refer to table of "Security Register Definition" for secu-
rity register bit definition and table of "4K-bit Secured OTP Definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit Se-
cured OTP mode, array access is not allowed.
Table 3. 4K-bit Secured OTP Definition
Address range
xxx000~xxx00F
xxx010~xxx1FF
Size
128-bit
3968-bit
Standard Factory Lock
ESN (electrical serial number)
N/A
Customer Lock
Determined by customer
P/N: PM1736
REV. 1.8, DEC. 26, 2011
11
11 Page | ||
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