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부품번호 | H26M11001BAR 기능 |
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기능 | 1GB e-NAND | ||
제조업체 | Hynix | ||
로고 | |||
e-NAND
1GB e-NAND
H26M11001BAR
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 1.0 / Sep. 2009
1
e-NAND
1.2 System Features
● JEDEC JESD84 V4.3 compatible
● Backward compatible with earlier JESD84
● Maximum data rate with up to 52MB/sec interface speed ( using 8 parallel data lines )
● Voltage Range :
Communication
Memory Access
Voltage
1.7 - 1.95 or 2.7 - 3.6
2.7 - 3.6
● e-NAND supported clock frequencies 0~20MHz, 0~26MHz, 0~52MHz
● e-NAND support for three different data bus width modes: 1bit(default), 4bit and 8 bit
● Correction of memory field errors
● Simple erase mechanism
● Password Protection of e-NAND
1.2.1 Product List
PART NUMBER
H26M11001BAR
DENSITY
1GB
JEDEC JESD84 SPEC
V4.3
PACKAGE
169-FBGA (12x16x1.3)
Rev 1.0 / Sep. 2009
4
4페이지 e-NAND
1.6.5 Read and Write Operations
The e-NAND supports two read/write modes.
Single Block Mode
In this mode the host read or write one data block in a pre-specified length block transmission is protected with 16bit
CRC which is generated by the sending unit and checked by the receiveing unit. Misalignment is not allowed. Every data
block must be contained in a single memroy sector. The block length for write opertaion must be identical to the sector
size and the start address aligned to a sector boundary.
Multiple Block Mode
This mode is similar to the single block mode, but the host can read/write multiple data blocks (all have the same length)
which will be stored or retrived from contiguous memory addresses starting at the address specified in the command.
The operation is terminated with a stop transmission command. Misalignment and block length restrictions apply to multiple
blocks as well and are identical to the single block read/write operations. Multiple block read with pre-defined block is sup-
ported.
1.6.6 Data Protection in the e-NAND
Every sector is protected with an Error Correction Code (ECC). The ECC is generated (in the e-NAND) when the
sectors are written and validated when the data is read. If defects are found, the data is corrected prior to transmission to
the host. The e-NAND can be considered error free and no additional data protection is needed. However, if an application
uses additional, external, ECC protection, the data oragnization is defined in the user writeable section of the CSD register.
1.6.7 Erase
The smallest erasable unit in the e-NAND is a erase group. In order to speed up the erase procedure, multiple erase groups
can be erased in the same time. The erase operation is divided into two stages.
Tagging - Selecting the Sectors for Erasing
To facilitate selection, a first command with the starting address is followed by a second command with the final address,
and all erase groups within this range will be selected for erase.
Erasing - Starting the Erase Process
Tagging can address erase groups. An arbitrary selection of erase groups may be erased at one time. Tagging and erasing
must follow a strict command sequence (refer to the e-NAND standard sepcification for datails).
1.6.8 Write Protection
Two-card level write-protection options are available: permanent and temporary. Both can be set using the PROGRAM_CSD
command (refer to CSD Programming, Section 4.2.8). The permanent write protect bit, once set, cannot be clearded. This
feature is implemented in the e-NAND controller firmware and not with a physical OTP cell.
1.6.9 Copy Bit
The content of an e-NAND can be marked as an original or a copy using the copy bit in the CSD register. Once the Copy bit
is set (maked as original) it cannot be cleared. The Copy bit of the e-NAND is programmed (during test and formatting on
the manufacturing floor) as a copy. The e-NAND can be purchased with the copy bit set (copy) or cleared, indicating the
card is a master. The One Time Programmable (OTP) characteristic of the Copy bit is implemented in the e-NAND controller
firmware and not with a physical OTP cell.
Rev 1.0 / Sep. 2009
7
7페이지 | |||
구 성 | 총 70 페이지수 | ||
다운로드 | [ H26M11001BAR.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
H26M11001BAR | 1GB e-NAND | Hynix |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |