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R1RW0404DGE-2PR 데이터시트 PDF




Renesas에서 제조한 전자 부품 R1RW0404DGE-2PR은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 R1RW0404DGE-2PR 자료 제공

부품번호 R1RW0404DGE-2PR 기능
기능 4M High Speed SRAM
제조업체 Renesas
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R1RW0404DGE-2PR 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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R1RW0404DGE-2PR 데이터시트, 핀배열, 회로
R1RW0404D Series
4M High Speed SRAM (1-Mword × 4-bit)
REJ03C0115-0100Z
Rev. 1.00
Mar.12.2004
Description
The R1RW0404D is a 4-Mbit high speed static RAM organized 1-Mword × 4-bit. It has realized high
speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit
designing technology. It is most appropriate for the application which requires high speed and high density
memory, such as cache and buffer memory in system. The R1RW0404D is packaged in 400-mil 32-pin
SOJ for high density surface mounting.
Features
Single supply: 3.3 V ± 0.3 V
Access time: 12 ns (max)
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Directly TTL compatible
All inputs and outputs
Operating current: 100 mA (max)
TTL standby current: 40 mA (max)
CMOS standby current: 5 mA (max)
: 0.8 mA (max) (L-version)
Data retention current: 0.4 mA (max) (L-version)
Data retention voltage: 2 V (min) (L-version)
Center VCC and VSS type pin out
Rev.1.00, Mar.12.2004, page 1 of 11




R1RW0404DGE-2PR pdf, 반도체, 판매, 대치품
R1RW0404D Series
Operation Table
CS# OE# WE# Mode
H × × Standby
L H H Output disable
L L H Read
L H L Write
L L L Write
Note:
H:
V , L:
IH
V,
IL
×:
V or V
IH IL
V current
CC
I ,I
SB SB1
ICC
ICC
ICC
ICC
I/O
High-Z
High-Z
DOUT
DIN
DIN
Ref. cycle
Read cycle (1) to (3)
Write cycle (1)
Write cycle (2)
Absolute Maximum Ratings
Parameter
Symbol
Value
Supply voltage relative to VSS
Voltage on any pin relative to VSS
Power dissipation
Operating temperature
VCC
VT
P
T
Topr
0.5 to +4.6
0.5*1 to VCC + 0.5*2
1.0
0 to +70
Storage temperature
Tstg 55 to +125
Storage temperature under bias
Tbias
10 to +85
Notes: 1. VT (min) = 2.0 V for pulse width (under shoot) 6 ns.
2. VT (max) = VCC + 2.0 V for pulse width (over shoot) 6 ns.
Unit
V
V
W
°C
°C
°C
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter
Symbol Min
Typ
Supply voltage
VCC*3
3.0
3.3
VSS*4
0
0
Input voltage
VIH 2.0
VIL 0.5*1
Notes:
1.
V
IL
(min)
=
2.0
V
for
pulse
width
(under
shoot)
6
ns.
2. VIH (max) = VCC + 2.0 V for pulse width (over shoot) 6 ns.
3. The supply voltage with all VCC pins must be on the same level.
4. The supply voltage with all V pins must be on the same level.
SS
Max
3.6
0
VCC + 0.5*2
0.8
Unit
V
V
V
V
Rev.1.00, Mar.12.2004, page 4 of 11

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R1RW0404DGE-2PR 전자부품, 판매, 대치품
R1RW0404D Series
Write Cycle
R1RW0404D
-2
Parameter
Symbol Min
Max Unit Notes
Write cycle time
t 12
WC
ns
Address valid to end of write
t8
AW
ns
Chip select to end of write
tCW 8
ns 9
Write pulse width
tWP 8
ns 8
Address setup time
tAS 0
ns 6
Write recovery time
tWR 0
ns 7
Data to write time overlap
t6
DW
ns
Data hold from write time
t0
DH
ns
Write disable to output in low-Z
tOW 3
ns 1
Output disable to output in high-Z
tOHZ
6
ns 1
Write enable to output in high-Z
tWHZ
6
ns 1
Notes: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is
sampled and not 100% tested.
2. Address should be valid prior to or coincident with CS# transition low.
3. WE# and/or CS# must be high during address transition time.
4. If CS# and OE# are low during this period, I/O pins are in the output state. Then, the data input
signals of opposite phase to the outputs must not be applied to them.
5. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE#
transition, output remains a high impedance state.
6. tAS is measured from the latest address transition to the later of CS# or WE# going low.
7. tWR is measured from the earlier of CS# or WE# going high to the first address transition.
8. A write occurs during the overlap of a low CS# and a low WE#. A write begins at the latest
transition among CS# going low and WE# going low. A write ends at the earliest transition
among CS# going high and WE# going high. t is measured from the beginning of write to the
WP
end of write.
9. tCW is measured from the later of CS# going low to the end of write.
Rev.1.00, Mar.12.2004, page 7 of 11

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관련 데이터시트

부품번호상세설명 및 기능제조사
R1RW0404DGE-2PR

4M High Speed SRAM

Renesas
Renesas

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