PDF AS8C801801-QC150N Data sheet ( Hoja de datos )

Número de pieza	AS8C801801-QC150N
Descripción	3.3V Synchronous ZBT SRAMs
Fabricantes	Alliance Semiconductor
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No Preview Available ! 256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs AS8C803601 AS8C801801 Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (READ/WRITE) control pin ◆ Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications ◆ 4-word burst capability (interleaved or linear) ◆ Individual byte write (BW1 - BW4) control (May tie active) ◆ Three chip enables for simple depth expansion ◆ 3.3V power supply (±5%) ◆ 3.3V I/O Supply (V DDQ) ◆ Power down controlled by ZZ input ◆ Packaged in a JEDEC standard 100-pin plastic thin quad flatpack (TQFP). Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. TheAS8C803601/801801 contain data I/O, address and control signal registers. Output enable is the only asynchronoussignal and can be used to disable the outputsat any given time. A Clock Enable(CEN) pin allows operation of the toAS8C803601/ 801801 be suspended as long as necessary. All synchronousinputs are ignored when (CEN)is high and the internal device registers will hold their previous values. There are three chip enable pins (CE1, CE2,CE2) that allow the user to deselect the device when desired. If anyone of these three are not asserted when ADV/LD is low, no new memoryoperation can be initiated. However, any pending data transfers (reads or writes) will be completed. The data bus will tri-state two cycles after chip is deselected or a write is initiated. TheAS8C803601/801801 have an on-chip burst counter. In the burst mode,the AS8C803601/801801 can provide fourcycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADVL/ D =LOW) or increment the internal burst counter Description The AS8C803601/801801 are3.3V high-speed 9,437,184 bit (9 Megabit) synchronous SRAMS. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and (ADV/LD = HIGH). The AS8C803601/801801 SRAM utilize IDT's latest high-performance CMOS process, andare packaged ina JEDEC Standard 14mm x 20mm 100- pin thin plastic quad flatpack (TQFP) . reads. Thus, they have been given the name ZBTMT, or Zero Bus Turnaround. Pin Description Summary A0-A18 Address Inputs CE1, CE2, CE2 OE R/W Chip Enables Output Enable Read/Write S ignal CEN Clock Enable BW1, BW2, BW3, BW4 Individual Byte Write Selects CLK ADV/LD Clock Advance burst address / Load new address LBO Linear / In terleaved B urst Order ZZ Sleep Mode I/O0-I/O31, I/OP1-I/OP4 Data Input / Output VDD, VDDQ Core P ower, I/ O Power VSS Ground Input Input Input Input Input Input Input Input Input Input I/O Supply Supply Synchronous Synchronous Asynchronous Synchronous Synchronous Synchronous N/A Synchronous Static Asynchronous Synchronous Static Static 5304 tbl 01 SEPTEMBER 2010 1 DSC-5304/07 1 page IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperatur e Ranges Recommended Operating Temperature and Supply Voltage Grade Ambient Temperature(1) VSS VDD VDDQ Commercial 0° C to +70° C 0V 3.3V±5% 3.3V±5% Industrial -40°C to +85°C 0V 3.3V±5% 3.3V±5% NOTES: 5304 tbl 05 1. During production testing, the case temperature equals the ambient temperature . Pin Configuration - 256K x 36 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/OP3 I/O16 I/O17 VDDQ VSS I/O18 I/O19 I/O20 I/O21 VSS VDDQ I/O22 I/O23 VDD(1) VDD VDD(1) VSS I/O24 I/O25 VDDQ VSS I/O26 I/O27 I/O28 I/O29 VSS VDDQ I/O30 I/O31 I/OP4 1 80 I/OP2 2 79 I/O15 3 78 I/O14 4 77 VDDQ 5 76 VSS 6 75 I/O13 7 74 I/O12 8 73 I/O11 9 72 I/O10 10 71 VSS 11 70 VDDQ 12 69 I/O9 13 68 I/O8 14 67 VSS 15 66 VDD(1) 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDD ZZ I/O7 I/O6 VDDQ VSS I/O5 I/O4 I/O3 I/O2 VSS VDDQ I/O1 I/O0 I/OP1 5304 drw 02 , Top View 100 TQFP NOTES: 1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage≥isVIH. 2. Pin 84 is reserved for a future 16M. 3. DNU= Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG pins: TMS, TDI, TDO and TCK. The current die revision allows these pins to be left unconnected, tied LOW (V SS), or tied HIGH (V DD). 6.542 5 Page AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Read Operation with Clock Enable Used(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE I/O n A0 H L L L X X X n+1 X X X X HXXX n+2 A1 H L L L X X X n+3 X X X X H X L Q0 n+4 X X X X H X L Q0 n+5 A2 H L L L X L Q0 n+6 A3 H L L L X L Q1 n+7 A4 H L L L X L Q2 Commercial Temperatur e Range Comments Address and Control meet setup Clock n+1 I gnored Clock V alid Clock Ignored, Data Q0 is on the bus. Clock Ignored, Data Q0 is on the bus. Address A0 Read o ut (bus trans.) Address A1 R ead o ut (bus trans.) Ad dress A2 Read o ut (bus trans.) NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L. Write Operation with Clock Enable Used(1) Cycle Address R/W ADV/LD CE(2) CEN BWx OE n A0 L L L L L X n+1 X XX X HXX n+2 A1 L L L L L X n+3 X X X X H X X n+4 X X X X H X X n+5 A2 L L L L L X n+6 A3 L L L L L X n+7 A4 L L L L L X I/O Comments X Address and Control meet setup. X Clock n+ 1 Ignored. X Clock Valid. X Clock Ignored. X Clock Ignored. D0 Write Data D0 D1 Write Data D1 D2 Write Data D2 NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE 2 = H. CE = H is defined as CE1 = H, CE2 = H or CE 2 = L. 11 11 Page

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