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R1RP0416DSB-2PR 데이터시트 PDF




Renesas에서 제조한 전자 부품 R1RP0416DSB-2PR은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 R1RP0416DSB-2PR 기능
기능 4M High Speed SRAM
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R1RP0416DSB-2PR 데이터시트, 핀배열, 회로
R1RP0416D Series
4M High Speed SRAM (256-kword × 16-bit)
REJ03C0108-0100Z
Rev. 1.00
Mar.12.2004
Description
The R1RP0416D Series is a 4-Mbit high speed static RAM organized 256-k word × 16-bit. It has realized
high speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit
designing technology. It is most appropriate for the application which requires high speed, high density
memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in
400-mil 44-pin plastic SOJ and 400-mil 44-pin plastic TSOPII.
Features
Single 5.0 V supply: 5.0 V ± 10%
Access time: 12 ns (max)
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Directly TTL compatible
All inputs and outputs
Operating current: 160 mA (max)
TTL standby current: 40 mA (max)
CMOS standby current: 5 mA (max)
: 1.0 mA (max) (L-version)
Data retention current: 0.5 mA (max) (L-version)
Data retention voltage: 2 V (min) (L-version)
Center VCC and VSS type pin out
Ordering Information
Type No.
R1RP0416DGE-2PR
R1RP0416DGE-2LR
R1RP0416DSB-2PR
R1RP0416DSB-2LR
Access time
12 ns
12 ns
12 ns
12 ns
Package
400-mil 44-pin plastic SOJ (44P0K)
400-mil 44-pin plastic TSOPII (44P3W-H)
Rev.1.00, Mar.12.2004, page 1 of 13




R1RP0416DSB-2PR pdf, 반도체, 판매, 대치품
R1RP0416D Series
Operation Table
CS# OE# WE# LB# UB# Mode
V current
CC
H × × × × Standby
I ,I
SB SB1
L H H × × Output disable ICC
L L H L L Read
ICC
L L H L H Lower byte read ICC
L L H H L Upper byte read ICC
L L HHH
ICC
L × L L L Write
ICC
L × L L H Lower byte write ICC
L
×
L
HL
Upper byte write I
CC
L × L HH
I
CC
Note: H: VIH, L: VIL, ×: VIH or VIL
I/O1I/O8
High-Z
High-Z
Output
Output
High-Z
High-Z
Input
Input
High-Z
High-Z
I/O9I/O16
High-Z
High-Z
Output
High-Z
Output
High-Z
Input
High-Z
Input
High-Z
Ref. cycle
Read cycle
Read cycle
Read cycle
Write cycle
Write cycle
Write cycle
Absolute Maximum Ratings
Parameter
Symbol
Value
Supply voltage relative to VSS
Voltage on any pin relative to V
SS
Power dissipation
Operating temperature
VCC
V
T
P
T
Topr
0.5 to +7.0
0.5*1
to
V
CC
+
0.5*2
1.0
0 to +70
Storage temperature
Tstg 55 to +125
Storage temperature under bias
Tbias
10 to +85
Notes: 1. VT (min) = 2.0 V for pulse width (under shoot) 6 ns.
2.
V
T
(max)
=
V
CC
+
2.0
V
for
pulse
width
(over
shoot)
6
ns.
Unit
V
V
W
°C
°C
°C
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter
Symbol
Min Typ
Supply voltage
VCC*3
4.5 5.0
VSS*4
00
Input voltage
VIH 2.2
VIL
0.5*1
Notes:
1.
V
IL
(min)
=
2.0
V
for
pulse
width
(under
shoot)
6
ns.
2. VIH (max) = VCC + 2.0 V for pulse width (over shoot) 6 ns.
3. The supply voltage with all VCC pins must be on the same level.
4. The supply voltage with all V pins must be on the same level.
SS
Max
5.5
0
VCC + 0.5*2
0.8
Unit
V
V
V
V
Rev.1.00, Mar.12.2004, page 4 of 13

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R1RP0416DSB-2PR 전자부품, 판매, 대치품
R1RP0416D Series
Write Cycle
R1RP0416D
-2
Parameter
Symbol Min Max Unit Notes
Write cycle time
tWC 12 ns
Address valid to end of write
t8
AW
ns
Chip select to end of write
t8
CW
ns 8
Write pulse width
t8
WP
ns 7
Byte select to end of write
tBW 8
ns
Address setup time
tAS 0
ns 5
Write recovery time
tWR 0
ns 6
Data to write time overlap
tDW 6
ns
Data hold from write time
tDH 0
ns
Write disable to output in low-Z
tOW 3
ns 1
Output disable to output in high-Z
tOHZ
6
ns 1
Write enable to output in high-Z
t
WHZ
6
ns 1
Notes: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is
sampled and not 100% tested.
2. If the CS# or LB# or UB# low transition occurs simultaneously with the WE# low transition or
after the WE# transition, output remains a high impedance state.
3. WE# and/or CS# must be high during address transition time.
4. If CS#, OE#, LB# and UB# are low during this period, I/O pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
5. tAS is measured from the latest address transition to the latest of CS#, WE#, LB# or UB# going
low.
6. tWR is measured from the earliest of CS#, WE#, LB# or UB# going high to the first address
transition.
7. A write occurs during the overlap of a low CS#, a low WE# and a low LB# or a low UB# (tWP). A
write begins at the latest transition among CS# going low, WE# going low and LB# going low or
UB# going low. A write ends at the earliest transition among CS# going high, WE# going high
and LB# going high or UB# going high.
8. tCW is measured from the later of CS# going low to the end of write.
Rev.1.00, Mar.12.2004, page 7 of 13

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R1RP0416DSB-2PR

4M High Speed SRAM

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