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R1RP0404D 데이터시트 PDF




Renesas에서 제조한 전자 부품 R1RP0404D은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 R1RP0404D 기능
기능 4M High Speed SRAM
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R1RP0404D 데이터시트, 핀배열, 회로
R1RP0404D Series
4M High Speed SRAM (1-Mword × 4-bit)
REJ03C0116-0100Z
Rev. 1.00
Mar.12.2004
Description
The R1RP0404D is a 4-Mbit high speed static RAM organized 1-Mword × 4-bit. It has realized high speed
access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing
technology. It is most appropriate for the application which requires high speed and high density memory,
such as cache and buffer memory in system. The R1RP0404D is packaged in 400-mil 32-pin SOJ for high
density surface mounting.
Features
Single 5.0 V supply: 5.0 V ± 10%
Access time 12 ns (max)
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Directly TTL compatible
All inputs and outputs
Operating current: 130 mA (max)
TTL standby current: 40 mA (max)
CMOS standby current: 5 mA (max)
: 1.0 mA (max) (L-version)
Data retention current: 0.5 mA (max) (L-version)
Data retention voltage: 2.0 V (min) (L-version)
Center VCC and VSS type pin out
Rev.1.00, Mar.12.2004, page 1 of 11




R1RP0404D pdf, 반도체, 판매, 대치품
R1RP0404D Series
Operation Table
CS# OE# WE# Mode
H × × Standby
L H H Output disable
L L H Read
L H L Write
L L L Write
Note: H: VIH, L: VIL, ×: VIH or VIL
V current
CC
I ,I
SB SB1
ICC
ICC
ICC
ICC
I/O
High-Z
High-Z
DOUT
DIN
DIN
Ref. cycle
Read cycle (1) to (3)
Write cycle (1)
Write cycle (2)
Absolute Maximum Ratings
Parameter
Symbol
Value
Supply voltage relative to VSS
Voltage on any pin relative to VSS
Power dissipation
Operating temperature
VCC
VT
PT
Topr
0.5 to +7.0
0.5*1 to VCC + 0.5*2
1.0
0 to +70
Storage temperature
Tstg 55 to +125
Storage temperature under bias
Tbias
10 to +85
Notes:
1.
V
T
(min)
=
2.0
V
for
pulse
width
(under
shoot)
6
ns.
2. VT (max) = VCC + 2.0 V for pulse width (over shoot) 6 ns.
Unit
V
V
W
°C
°C
°C
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter
Symbol Min
Typ
Supply voltage
VCC*3
4.5
5.0
VSS*4
0
0
Input voltage
VIH 2.2
V
IL
0.5*1
Notes:
1.
V
IL
(min)
=
2.0
V
for
pulse
width
(under
shoot)
6
ns.
2. VIH (max) = VCC + 2.0 V for pulse width (over shoot) 6 ns.
3. The supply voltage with all VCC pins must be on the same level.
4. The supply voltage with all V pins must be on the same level.
SS
Max
5.5
0
VCC + 0.5*2
0.8
Unit
V
V
V
V
Rev.1.00, Mar.12.2004, page 4 of 11

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R1RP0404D 전자부품, 판매, 대치품
R1RP0404D Series
Write Cycle
R1RP0404D
-2
Parameter
Symbol Min
Max Unit Notes
Write cycle time
tWC 12 ns
Address valid to end of write
t8
AW
ns
Chip select to end of write
t8
CW
ns 9
Write pulse width
t8
WP
ns 8
Address setup time
tAS 0
ns 6
Write recovery time
tWR 0
ns 7
Data to write time overlap
tDW 6
ns
Data hold from write time
tDH 0
ns
Write disable to output in low-Z
tOW
3
ns 1
Output disable to output in high-Z
tOHZ
6
ns 1
Write enable to output in high-Z tWHZ
6
ns 1
Notes: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is
sampled and not 100% tested.
2. Address should be valid prior to or coincident with CS# transition low.
3. WE# and/or CS# must be high during address transition time.
4. If CS# and OE# are low during this period, I/O pins are in the output state. Then, the data input
signals of opposite phase to the outputs must not be applied to them.
5. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE#
transition, output remains a high impedance state.
6. t is measured from the latest address transition to the later of CS# or WE# going low.
AS
7. tWR is measured from the earlier of CS# or WE# going high to the first address transition.
8. A write occurs during the overlap of a low CS# and a low WE#. A write begins at the latest
transition among CS# going low and WE# going low. A write ends at the earliest transition
among CS# going high and WE# going high. tWP is measured from the beginning of write to the
end of write.
9. tCW is measured from the later of CS# going low to the end of write.
Rev.1.00, Mar.12.2004, page 7 of 11

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