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PDF N2DS51216DS Data sheet ( Hoja de datos )
| Número de pieza | N2DS51216DS | |
| Descripción | 512Mb DDR SDRAM | |
| Fabricantes | Elixir | |
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NT5DS64M8DS
N2DS51216DS
512Mb DDR SDRAM
Preliminary
Feature
CAS Latency Frequency
Speed Sorts
DDR-333
-6K
DDR400
-5T
CL-tRCD-tRP
2.5-3-3 3-3-3
CL=2
266
266
Speed CL=2.5 333
333
CL=3
333
400
Units
tCK
Mbps
Power Supply Voltage:
VDD=VDDQ=2.5V±0.2V (DDR-333)
VDD=VDDQ=2.6V±0.1V (DDR-400/500)
4 internal memory banks for concurrent operation.
CAS Latency: 2, 2.5 and 3
Double Data Rate Architecture
Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver.
Commercial grade device support 0℃~70℃ Operating
Temperature (-6K/5T)
2KB page size for all configurations.
DQS is edge-aligned with data for reads and is
center-aligned with data for WRITEs
Differential clock inputs (CK and )
Data mask (DM) for write data
DLL aligns DQ and DQS transition with CK transitions.
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Burst Lengths: 2, 4 or 8
Auto Pre-charge option for each burst access
Auto-Refresh and Self-Refresh Mode
7.8 µs max. Average Periodic Refresh Interval
2.5V (SSTL_2 compatible) I/O
RoHS and Halogen-Free compliance
Packages: 66 pin TSOPII
REV 0.1
11/2012
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1 page  
NT5DS64M8DS
N2DS51216DS
512Mb DDR SDRAM
Preliminary
Input / Output Functional Description
Symbol
Type
Function
CK,
CKE
, ,
DM, LDM, UDM
Input
Input
Input
Input
Input
Clock: CK and are differential clock inputs. All address and control input signals are sampled on the crossing of
the positive edge of CK and negative edge of . Output (read) data is referenced to the crossings of CK and
(both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and
output drivers. Taking CKE LOW provides PRE-CHARGE POWER--DOWN and SELF REFRESH operation (all
banks idle), or ACTIVE POWER--DOWN (row ACTIVE in any bank). CKE is synchronous for POWER-- DOWN
entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output
disable. CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, CK
and CKE are disabled during POWER--DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH.
CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after Vdd is applied upon 1st power up. After VREF
has become stable during the power on and initialization sequence, it must be maintained for proper operation of
the CKE receiver. For proper self--refresh entry and exit, VREF must be maintained to this input The standard
pinout includes one CKE pin. Optional pinouts include CKE0 and CKE1 on different pins, to facilitate device
stacking.
Chip Select: All commands are masked when is registered high. provides for external rank selection on
systems with multiple memory ranks. is considered part of the command code.
Command Inputs: , and (along with ) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along
with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input
only, the DM loading matches the DQ and DQS loading. For the X16, LDM corresponds to the data on DQ0--DQ7;
UDM corresponds to the data on DQ8--DQ15. DM may be driven high, low, or floating during READs.
BA0 – BA1
Input
Bank Address Inputs: BA# defines to which bank an Active, Read, Write or Pre-charge command is being
applied.
A0 – A12
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO
PRE-CHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective
bank. A10 is sampled during a pre-charge command to determine whether the PRE-CHARGE applies to one bank
(A10 LOW) or all banks (A10 HIGH). If only one bank is to be pre-charged, the bank is selected by BA0, BA1. The
address inputs also provide the op--code during a MODE REGISTER SET command. BA0 and BA1 define which
mode register is loaded during the MODE REGISTER SET command (MRS or EMRS).
DQ Input/output Data Bus: Inputs/Output
DQS, ()
LDQS, (),
UDQS,()
Data Strobe: Output with read data, input with write data. Edge--aligned with read data,
Input/output centered in write data. Used to capture write data. For the X16, LDQS corresponds to the
data on DQ0--DQ7; UDQS corresponds to the data on DQ8--DQ15.
RDQS, ()
Read Data Strobe: For x8 components a RDQS and pair can be enabled via EMRS(1) for real timing.
Input/output RDQS and is not support x16 components. RDQS and are edge-aligned with real data. If enable
RDQS and then DM function will be disabled.
NC
VDDQ
VSSQ
VDD
Supply
Supply
Supply
No Connect: No internal electrical connection is present.
DQ Power Supply: 2.5V ± 0.2V (-6K); VDD=VDDQ=2.6V±0.1V (-5T)
DQ Ground
Power Supply: 2.5V ± 0.2V (-6K); VDD=VDDQ=2.6V±0.1V (-5T)
VSS
VREF
Supply
Supply
Ground
SSTL_2 reference voltage
REV 0.1
11/2012
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5 Page 
NT5DS64M8DS
N2DS51216DS
512Mb DDR SDRAM
Preliminary
Burst Definition
Burst Length
2
4
8
Starting Colume Address
A2 A1
A0
--
0
--
1
-0
0
-0
1
-1
0
-1
1
00
0
00
1
01
0
01
1
10
0
10
1
11
0
11
1
Order of Accesses Within a Burst
Type=Sequential
Type=Interleaved
0-1 0-1
1-0 1-0
0-1-2-3
0-1-2-3
1-2-3-0
1-0-3-2
2-3-0-1
2-3-0-1
3-0-1-2
3-2-1-0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Notes:
1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the
block.
2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access
within the block.
3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access
within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access
wraps within the block.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as
the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst
length, the burst type and the starting column address, as shown in Burst Definition.
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command
and the availability of the first burst of output data. The latency can be programmed 2 or 2.5 clocks for
DDR266/333 and 3 clocks for DDR400/450/500.
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally
coincident with clock edge n + m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
REV 0.1
11/2012
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11 Page | ||
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