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부품번호 K4T1G084QF 기능
기능 1Gb F-die DDR2 SDRAM
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K4T1G084QF 데이터시트, 핀배열, 회로
Rev. 1.2, Jul. 2011
K4T1G044QF
K4T1G084QF
K4T1G164QF
1Gb F-die DDR2 SDRAM
60FBGA/84FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
2011 Samsung Electronics Co., Ltd. All rights reserved.
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K4T1G084QF pdf, 반도체, 판매, 대치품
K4T1G044QF
K4T1G084QF
K4T1G164QF
1. Ordering Information
Organization
256Mx4
128Mx8
64Mx16
DDR2-800 5-5-5
K4T1G044QF-BCE7
K4T1G084QF-BCE7
K4T1G164QF-BCE7
NOTE :
1. Speed bin is in order of CL-tRCD-tRP.
2. 12digit, "B" stands for flip chip FBGA PKG.
datasheet
DDR2-800 6-6-6
K4T1G044QF-BCF7
K4T1G084QF-BCF7
K4T1G164QF-BCF7
Rev. 1.2
DDR2 SDRAM
DDR2-667 5-5-5
K4T1G044QF-BCE6
K4T1G084QF-BCE6
K4T1G164QF-BCE6
Package
60 FBGA
60 FBGA
84 FBGA
2. Key Features
Speed
CAS Latency
tRCD(min)
tRP(min)
tRC(min)
DDR2-800 5-5-5
5
12.5
12.5
57.5
DDR2-800 6-6-6
6
15
15
60
DDR2-667 5-5-5
5
15
15
60
Units
tCK
ns
ns
ns
• JEDEC standard VDD = 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5, 6
• Programmable Additive Latenc y: 0, 1, 2, 3, 4, 5
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an
optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support
- 50ohm ODT
- High Temperature Self-Refresh rate enable
• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at
85°C < TCASE < 95 °C
• All of products are Lead-Free, Halogen-Free, and RoHS compliant
The 1Gb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 8banks, 16Mbit
x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks device. This synchronous
device achieves high speed double-data-rate transfer rates of up to 800Mb/
sec/pin (DDR2-800) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM fea-
tures such as posted CAS with additive latency, write latency = read latency
- 1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination.
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. For example, 1Gb(x8) device
receive 14/10/3 addressing.
The 1Gb DDR2 device operates with a single 1.8V ± 0.1V power supply
and 1.8V ± 0.1V VDDQ.
The 1Gb DDR2 device is available in 60ball FBGA(x4/x8) and in 84ball
FBGA(x16).
NOTE :
1. This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device Operation & Timing Dia-
gram”.
2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
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K4T1G084QF 전자부품, 판매, 대치품
K4T1G044QF
K4T1G084QF
K4T1G164QF
datasheet
Rev. 1.2
DDR2 SDRAM
3.3 x16 Package Pinout (Top view) : 84ball FBGA Package
1
2
3 456 7
8
9
A VDD NC VSS
B
DQ14
VSSQ
UDM
C VDDQ DQ9 VDDQ
D
DQ12
VSSQ
DQ11
E VDD NC VSS
F
DQ6
VSSQ
LDM
G VDDQ DQ1 VDDQ
H
DQ4
VSSQ
DQ3
J
VDDL
VREF
VSS
K
CKE
WE
L BA2 BA0 BA1
M
A10/AP
A1
N VSS
A3
A5
P A7 A9
R VDD A12
NC
VSSQ
UDQS
VDDQ
DQ10
VSSQ
LDQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
UDQS
VSSQ
DQ8
VSSQ
LDQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
NC
VDDQ
DQ15
VDDQ
DQ13
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT
VDD
VSS
NOTE : VDDL and VSSDL are power and ground for the DLL. It is recommended that they be isolated on the device from VDD, VDDQ, VSS, and VSSQ.
Ball Locations (x16)
Populated ball
Ball not populated
Top view
(See the balls through package)
123456789
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
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