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부품번호 M2Y1G64TU88G7B-AC 기능
기능 Unbuffered DDR2 SDRAM DIMM
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M2Y1G64TU88G7B-AC 데이터시트, 핀배열, 회로
M2Y1G64TU88G7B / M2Y2G64TU8HG5B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Preliminary
240pin Unbuffered DDR2 SDRAM MODULE
Based on 128Mx8 DDR2 SDRAM G-die
Features
Performance:
PC2-5300 PC2-6400 PC2-8500
Speed Sort
-3C -AC -BD Unit
DIMM  Latency*
5
5
6
f CK Clock Frequency 333 400 533 MHz
t CK Clock Cycle
3
2.5
1.875
ns
f DQ DQ Burst Frequency
667
800
1066
Mbps
Programmable Operation:
JEDEC Standard 240-pin Dual In-Line Memory Module
- Device  Latency: 3, 4, 5, 6
128Mx64 and 256Mx64 DDR2 Unbuffered DIMM based on
- Burst Length: 4, 8
Elixir 128Mx8 DDR2 SDRAM G-die component
• Auto Refresh (CBR) and Self Refresh Modes
Double Data Rate architecture; two data transfer per clock cycle
• Automatic and controlled precharge commands
Differential bi-directional data strobe (DQS & )
14/10/1 Addressing (row/column/rank) 1GB
DQS is edge-aligned with data for reads and is center-aligned
14/10/2 Addressing (row/column/rank) 2GB
with data for writes
• Serial Presence Detect
Differential clock inputs (CK & )
• On Die Termination (ODT)
Intended for 333MHz/400MHz applications
OCD impedance adjustment.
• Inputs and outputs are SSTL-18 compatible
• Gold contacts
VDD = VDDQ = 1.8V ± 0.1V
• 7.8 μs Max. Average Periodic Refresh Interval
SDRAMs in 60-ball BGA Package
• RoHs Compliance.
Description
M2Y1G64TU88G7B and M2Y2G64TU8HG5B are 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Unbuffered Dual In-Line
Memory Module (UDIMM), organized as one rank 128Mx64 and two ranks 256Mx64 high-speed memory array. M2Y1G64TU88G7B
uses eight 128Mx8 DDR2 SDRAMs and M2Y2G64TU8G5B uses sixteen 128Mx8 DDR2 SDRAMs in BGA packages. These DIMMs are
manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes
electrical variation between suppliers. All Elixir DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long
space-saving footprint.
The DIMM is intended for use in applications operating up to 333MHz (or 400MHz/533MHz) clock speeds and achieves high-speed data
transfer rates of up to 667Mbps (or 800Mbps/1066Mbps). Prior to any access operation, the device  latency and burst / length
/operation type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0, BA1 and BA2 using the mode register
set cycle.
The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of
serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
REV 0.1
01/2010
1
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.




M2Y1G64TU88G7B-AC pdf, 반도체, 판매, 대치품
M2Y1G64TU88G7B / M2Y2G64TU8HG5B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Preliminary
Input/Output Functional Description
Symbol
Type Polarity
Function
CK0, CK1, CK2
(SSTL)
Positive
Edge
The positive line of the differential pair of system clock inputs which drives the input to
the on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the
rising edge of their associated clocks.
, , 
(SSTL)
Negative The negative line of the differential pair of system clock inputs which drives the input to
Edge the on-DIMM PLL.
CKE0, CKE1
(SSTL)
Active
High
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode. CKE1 apply on 2GB UDIMM only.
, 
, , 
(SSTL)
(SSTL)
Active
Low
Active
Low
Enables the associated SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue.  apply on 2GB UDIMM only.
When sampled at the positive rising edge of the clock, , ,  define the
operation to be executed by the SDRAM.
VREF
Supply
Reference voltage for SSTL-18 inputs
VDDQ
Supply
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
ODT0, ODT1
BA0 BA2
Input
(SSTL)
Active
High
On-Die Termination control signals. ODT1 apply on 2GB UDIMM only.
- Selects which SDRAM bank is to be active.
A0 - A9
A10/AP
A11 - A13
(SSTL)
During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
-
invoke Autoprechargeoperation at the end of the Burst Read or Write cycle. If AP is
high, Autoprecharge’s selected and BA0/BA1 defines the bank to be precharged. If AP is
low, autoprecharge is disabled. During a Precharge command cycle, AP is used in
conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks
will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are
used to define which bank to pre-charge.
DQ0 DQ63
(SSTL)
Active
High
Data and Check Bit Input /Output pins.
VDD, VSS
DQS0 DQS8
 
Supply
(SSTL)
Power and ground for the DDR2 SDRAM input buffers and core logic
Negative
and
Positive
Data strobe for input and output data
Edge
DM0 DM8
Input
Active
High
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation if
it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits
CB0-CB7, and is not used on x64 modules.
SA0 SA2
-
Address inputs. Connected to either VDD or VSS on the system board to configure the
Serial Presence Detect EEPROM address.
SDA
-
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V DD to act as a pull-up.
SCL
-
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V DD to act as a pull-up.
V DDSPD
Supply
Serial EEPROM positive power supply.
REV 0.1
01/2010
4
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

4페이지










M2Y1G64TU88G7B-AC 전자부품, 판매, 대치품
M2Y1G64TU88G7B / M2Y2G64TU8HG5B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Preliminary
Absolute Maximum Ratings
Symbol
Parameter
Rating
Units
VIN, VOUT Voltage on any pin relative to Vss
-0.5 to 2.3
V
VDDQ
Voltage on VDDQ supply relative to Vss
-0.5 to 2.3
V
VDDQL
Voltage on VDDQL supply relative to Vss
-0.5 to 2.3
V
VDD Voltage on VDD supply relative to Vss
-1.0 to +2.3
V
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Operating Conditions
Symbol
Parameter
TCASE
Operating Temperature (Ambient)
TSTG
Storage Temperature (Plastic)
IL Short Circuit Output Current
Note:
1.
2.
3.
Case temperature is measured at top and center side of any DRAMs.
tCASE > 85°C tREFI = 3.9 μs
All DRAM specification only support 0°C < tCASE < 85°C
Rating
0 to 95
-55 to 100
-5 to 5
Units
°C
°C
Μa
Note
1,2,3
DC Electrical Characteristics and Operating Conditions
(TCASE = 0 °C ~ 85 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See AC Characteristics)
Symbol
Parameter
Min
Max
Units Notes
VDD Supply Voltage
1.7 1.9 V 1
VDDQ Supply Voltage for Output
1.7 1.9 V 1, 3
VDDL
Supply Voltage for VDDQL
1.7 1.9 V 3
VREF
VTT
Input Reference Voltage
Termination Voltage
0.49VDDQ 0.51VDDQ
VREF 0.04 VREF + 0.04
Mv
V
2
4
VIH (DC)
VIL (DC)
Input High (Logic1) Voltage
Input Low (Logic0) Voltage
VREF + 0.125 VDDQ + 0.3
-0.3 VREF 0.125
V
V
Note:
1. Inputs are not recognized as valid until VREF stabilizes.
2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on VREF may not exceed 2% of the DC value.
3. VDDQ tracks with VDD, VDDL tracks with VDD.
4. VTT of transmitting device track VREF of receiving device.
Environmental Parameters
Symbol
Parameter
Rating
Units
Note
TOPR
Module Operating Temperature Range (ambient)
0 to 55
°C 3
HOPR
Operating Humidity (relative)
10 to 90
%
TSTG
Storage Temperature (Plastic)
-55 to 100
°C 1
HSTG
Storage Humidity (without condensation)
5 to 95
%1
PBAR
Barometric Pressure (operating & storage)
105 to 69
K Pascal 1,2
Note:
1.
2.
3.
Stresses greater than those listed may cause permanent damage to the device. This is a tress rating only and device
functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Up to 9850 ft.
The component maximum case temperature shall not exceed the value specified in the component spec.
REV 0.1
01/2010
7
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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M2Y1G64TU88G7B-AC

Unbuffered DDR2 SDRAM DIMM

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