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HC-5560 데이터시트 PDF




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부품번호 HC-5560 기능
기능 PCM Transcoder
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HC-5560 데이터시트, 핀배열, 회로
Data Sheet
HC-5560
January 1997 File Number 2887.2
PCM Transcoder
The HC-5560 digital line transcoder provides encoding and
decoding of pseudo ternary line code substitution schemes.
Unlike other industry standard transcoders, the HC-5560
provides four worldwide compatible mode selectable code
substitution schemes, including HDB3 (High Density Bipolar
3), B6ZS, B8ZS (Bipolar with 6 or 8 Zero Substitution) and
AMI (Alternate Mark Inversion).
The HC-5560 is fabricated in CMOS and operates from a
single 5V supply. All inputs and outputs are TTL compatible.
Application Note #573, “The HC-5560 Digital Line
Transcoder,” by D.J. Donovan is available.
Ordering Information
PART TEMP. RANGE
NUMBER (oC) PACKAGE
PKG. NO.
HC3-5560-5
0 to 70 20 Ld PDIP E20.3
Pinout
HC-5560
(PDIP)
TOP VIEW
FORCE AIS 1
MODE SELECT 1 2
NRZ DATA IN 3
CLK ENC 4
MODE SELECT 2 5
NRZ DATA OUT 6
CLK DEC 7
RESET AIS 8
AIS 9
VSS 10
20 VDD
19 OUTPUT ENABLE
18 RESET
17 OUT1
16 OUT2
15 BIN
14 LOOP TEST ENABLE
13 AIN
12 CLOCK
11 ERROR
Features
• Single 5V Supply . . . . . . . . . . . . . . . . . . . . . . .10mA (Typ)
• Mode Selectable Coding Including:
- AMI (T1, T1C)
- B8ZS (T1)
- HDB3 (PCM30)
• North American and European Compatibility
• Simultaneous Encoding and Decoding
• Asynchronous Operation
• Loop Back Control
• Transmission Error Detection
• Alarm Indication Signal
• Replaces MJ1440, MJ1471 and TCM2201 Transcoders
Applications
• North American and European PCM Transmission Lines
where Pseudo Ternary Line Code Substitution Schemes
are Desired
• Any Equipment that Interfaces T1, T1C, T2 or PCM30
Lines Including Multiplexers, Channel Service Units,
(CSUs) Echo Cancellors, Digital Cross-Connects (DSXs),
T1 Compressors, etc.
• Related Literature
- AN573, The HC-5560 Digital Line Transcoder
Functional Diagram
MODE 1
SELECT 2
NRZ DATA IN
CLK ENC
OUTPUT
ENABLE
TRANSMITTER/
ENCODER
VDD
VSS
CLOCK
OUT 1
OUT 2
LOOP TEST
ENABLE
AIN
BIN
FORCE AIS
RESET
CLK DEC
RESET AIS
SWITCH
RECEIVER/
DECODER
NRZ DATA
OUT
AIS
DETECT
ERROR
DETECT
ERROR
AIS
69 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999




HC-5560 pdf, 반도체, 판매, 대치품
HC-5560
Pin Descriptions (Continued)
PIN NUMBER FUNCTION
DESCRIPTION
14 LTE Loop Test Enable, this pin selects between normal and loop back operation. A logic ‘0’ selects normal oper-
ation where encode and decode are independent and asynchronous. A logic ‘1’ selects a loop back condition
where OUT1 is internally connected to AIN and OUT2 is internally connected to BIN. A decode clock must
be supplied.
16, 17
OUT1, OUT2
Outputs representing the ternary encoded NRZ Data In signal for line transmission. OUT1 and OUT2 are in
return to zero form and are clocked out on the positive going edge of CLK ENC. The length of OUT1 and
OUT2 is set by the length of the positive clock pulse.
18
Reset
A logic ‘0’ on this pin resets all internal registers to zero. A logic ‘1’ allows normal operation of all internal
registers.
19 Output Enable A logic ‘1’ on this pin forces outputs OUT1 and OUT2 to zero. A logic ‘0’ allows normal operation.
20
VDD
Power to chip.
Functional Description
The HC-5560 TRANSCODER can be divided into six sec-
tions: transmission (coding), reception (decoding), error
detection, all ones detection, testing functions, and output
controls.
The transmitter codes a non-return to zero (NRZ) binary uni-
polar input signal (NRZ Data In) into two binary unipolar
return to zero (RZ) output signals (OUT1, OUT2). These out-
put signals represent the NRZ data stream modified accord-
ing to the selected encoding scheme (i.e., AMl, B8ZS, B6ZS,
HDB3) and are externally mixed together (usually via a tran-
sistor or transformer network) to create a ternary bipolar sig-
nal for driving transmission lines.
The receiver accepts as its input the ternary data from the
transmission line that has been externally split into two
binary unipolar return to zero signals (AIN and BIN). These
signals are decoded, according to the rules of the selected
line code into one binary unipolar NRZ output signal (NRz
Data Out).
The encoder and decoder sections of the chip perform inde-
pendently (excluding loopback condition) and may operate
simultaneously.
The Error output signal is active high for one cycle of CLK
DEC upon the detection of any bipolar violation in the
received AIN and BIN signals that is not part of the selected
line coding scheme. The bipolar violation is not removed,
however, and shows up as a pulse in the NRZ Data Out sig-
nal. In addition, the Error output signal monitors the received
AIN and BIN signals for a string of zeros that violates the
maximum consecutive zeros allowed for the selected line
coding scheme (i.e., 15 for AMI, 8 for B8ZS, 6 for B6ZS, and
4 for HDB3). ln the event that an excessive amount of zeros
is detected, the Error output signal will be active high for one
cycle of CLK DEC during the zero that exceeds the maxi-
mum number. In the case that a high level should simulta-
neously appear on both received input signals AIN and BIN a
logical one is assumed and appears on the NRZ Data Out
stream with the Error output active.
An input signal received at inputs AIN and BIN that consists
of all ones (or marks) is detected and signaled by a high
level at the Alarm Indication Signal (AlS) output. This is also
known as Blue Code. The AlS output is set to a high level
when less than three zeros are received during one period of
Reset AIS immediately followed by another period of Reset
AlS containing less than three zeros. The AIS output is reset
to a low level upon the first period of Reset AlS containing 3
or more zeros.
A logic high level on LTE enables a loopback condition
where OUT1 is internally connected to AIN and OUT2 is
internally connected to BIN (this disables inputs AIN and BIN
to external signals). In this condition, NRZ Data In appears
at NRZ Data Out (delayed by the amount of clock cycles it
takes to encode and decode the selected line code). A
decode clock must be supplied for this operation.
The output controls are Output Enable and Force AlS. These
pins allow normal operation, force OUT1 and OUT2 to zero,
or force OUT1 and OUT2 to output all ones (AIS condition).
Line Code Descriptions
AMl, Alternate Mark Inversion, is used primarily in North
American T1 (1.544MHz) and T1C (3.152MHz) carriers.
Zeros are coded as the absence of a pulse and ones are
coded alternately as positive or negative pulses. This type of
coding reduces the average voltage level to zero to eliminate
DC spectral components, thereby eliminating DC wander. To
simplify timing recovery, logic 1’s are encoded with 50% duty
cycle pulses.
e.g.,
PCM CODE
0 0 0 1 01 1 1 0 1 0 0 00 01
AMI CODE
To facilitate timing maintenance at regenerative repeaters
along a transmission path, a minimum pulse density of logic
1s is required. Using AMl, there is a possibility of long strings
of zeros and the required density may not always exist, lead-
ing to timing jitter and therefore higher error rates.
A method for insuring minimum logic 1 density by substituting
bipolar code in place of strings of 0s is called BNZS or Bipolar
72

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HC-5560 전자부품, 판매, 대치품
Timing Waveforms (Continued)
HC-5560
tFCL
CLK DEC
AIN, BIN
10%
1
fCL
90%
tRCL
50%
tS
50%
CLOCK
NRZ DATA OUT
50%
tDD
50%
tH
FIGURE 2. RECEIVER (DECODER) TIMING WAVEFORMS
CLK DEC
RESET AIS
50%
tH2
50%
tS2 tPD5
tS2
50%
50%
AIS OUTPUT
tPD4
50%
ERROR OUTPUT
50%
FIGURE 3. RESET AIS INPUT, AIS OUTPUT, ERROR OUTPUT
CLK DEC
RESET AIS
NRZ DATA OUT
AIS
FIGURE 4.
Two consecutive periods of Reset AIS, each containing less than three zeros, sets AIS to a logic ‘1’ and remains in a logic ‘1’ state
until a period of Reset AIS contains three or more zeros.
75

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부품번호상세설명 및 기능제조사
HC-5560

PCM Transcoder

Intersil Corporation
Intersil Corporation

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